Wafer structure and forming method thereof

A wafer and ladder structure technology, applied in the manufacture of electrical components, electrical solid devices, semiconductor/solid devices, etc., can solve problems such as damage to electrical pad metal materials, brittle solder bumps, poor stacking, etc., to achieve improved Reliability, improved stackability, yield and quality effects

Active Publication Date: 2009-09-16
ADVANCED SEMICON ENG INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

When the UBM layer 17 is sputtered on the polymer layer 15, the passivation layer 13 and the wafer 11, poor stacking tends to occur at the notches 16(1) and 16(2), resulting in solder bumps Poor joint quality with electrical pads
In a more serious situation, the materials of the electrical pad and the solder bump will diffuse each other at the place where the UBM layer 17 is poorly stacked, which will further cause brittle fracture of the solder bump, or the electrical pad metal Phenomenon of material damage (metal void)

Method used

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  • Wafer structure and forming method thereof
  • Wafer structure and forming method thereof
  • Wafer structure and forming method thereof

Examples

Experimental program
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no. 1 example

[0038] Please also refer to Figure 2A-2G , Figure 2A A schematic diagram illustrating a wafer according to a first embodiment of the present invention; Figure 2B shows that the second protective layer is formed on Figure 2A The schematic diagram on the first protective layer; Figure 2C Indicates that the adhesion layer is formed on Figure 2B The schematic diagram on the wafer and the second protective layer; Figure 2D The photoresist layer is shown formed in Figure 2C Schematic diagram on the adhesive layer of ; Figure 2E Shows barrier layer plating on Figure 2D Schematic diagram on the adhesive layer of ; Figure 2F Indicates that the wetting layer is formed in Figure 2E Schematic diagram on the barrier layer of ; Figure 2G draw Figure 2F Schematic diagram of removing the middle photoresist layer and part of the adhesive layer.

[0039] According to the method for forming a wafer structure according to the first embodiment of the present invention, a w...

no. 2 example

[0050] The difference between this embodiment and the above-mentioned first embodiment is that in this embodiment, a wetting layer is used to form a T-shaped or U-shaped plug. In addition, in the method for forming the wafer structure of this embodiment, the steps of providing a wafer, forming a second protective layer, forming an adhesive layer, and forming a photoresist layer are performed in the same manner at first, and these steps are the same as those of the first embodiment (such as Figure 2A-2D shown), and will not be repeated here.

[0051] Please also refer to Figure 4A and 4B , Figure 4A A schematic diagram showing the formation of the barrier layer on the adhesive layer according to the second embodiment of the present invention; Figure 4B Indicates that the wetting layer is formed in Figure 4A Schematic diagram of the barrier layer. The forming method of this embodiment is followed by a step of electroplating a barrier layer. Such as Figure 4A As show...

no. 3 example

[0057] The difference between this embodiment and the above-mentioned first embodiment mainly lies in the configuration of the photoresist layer and the method of forming the UBM layer, and the rest of the similarities will be omitted for brevity. Please also refer to Figures 6A-6G , Figure 6A A schematic diagram showing a wafer and a second protective layer according to a third embodiment of the present invention; Figure 6B Indicates that the adhesion layer is formed on Figure 6A The schematic diagram on the wafer and the second protective layer; Figure 6C shows that the barrier layer is formed in Figure 6B Schematic diagram on the adhesive layer of ; Figure 6D Indicates that the wetting layer is formed in Figure 6C Schematic diagram on the barrier layer of ; Figure 6E The photoresist layer is shown formed in Figure 6D Schematic diagram on the wetting layer of ; Figure 6F Draw to remove Figure 6E Schematic diagram of the wetting layer, barrier layer, and ...

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Abstract

A wafer structure and its forming method. First, a wafer with pads and a first protection layer is provided. The first protection layer covers the wafer and has a first opening exposing part of the pads. Secondly, a second protection layer is formed on the first protection layer, the second protection layer has a second opening exposing a portion of the pad and the first protection layer. The second opening is larger than the first opening, and edges of the two openings form a stepped structure. Next, an adhesive layer is formed on the pads, the ladder structure and the second protective layer, and a photoresist layer is formed on the adhesive layer. The photoresist layer has a third opening corresponding to the pads and exposing part of the adhesive layer. Next, a plating barrier layer overlies the exposed adhesion layer and forms a wetting layer on the barrier layer. Next, the photoresist layer and the adhesive layer not covered by the barrier layer are removed. Then, a solder layer is printed on the wetting layer.

Description

【Technical field】 [0001] The present invention relates to a wafer structure and its forming method, and in particular to a wafer structure with an electroplating layer and its forming method. 【Background technique】 [0002] Electronic products are becoming more and more popular among consumers in the market. In order to meet the market demand, the industry is all committed to developing multi-functional products. With the multi-functionalization of electronic products, the number of semiconductor packages contained therein is also increasing. However, the volume and weight of products are gradually miniaturized, which makes the semiconductor package more severely tested in terms of heat dissipation and operational stability. This further highlights the importance of the quality of the semiconductor package. [0003] In the packaging technology of semiconductor packages, common chip connection technologies include flipchip, wire bonding, and tape automated bonding to electr...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/60H01L23/485
CPCH01L24/11H01L2224/11H01L2924/351H01L2924/00H01L2924/00012
Inventor 温小周
Owner ADVANCED SEMICON ENG INC
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