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DRAM stacked package, DIMM, and semiconductor manufacturing method

A stacked package and test device technology, applied in the direction of static memory, electronic circuit testing, instruments, etc., can solve problems such as not considered, and achieve the effect of preventing the decline of yield and reducing product prices

Inactive Publication Date: 2009-12-30
HITACHI LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, in order to increase the frequency of address, command, and data input and output to the same level as that of a chip product, it is indispensable to use an interface chip, but this point has not been considered in the above-mentioned prior art.

Method used

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  • DRAM stacked package, DIMM, and semiconductor manufacturing method
  • DRAM stacked package, DIMM, and semiconductor manufacturing method
  • DRAM stacked package, DIMM, and semiconductor manufacturing method

Examples

Experimental program
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Effect test

no. 1 Embodiment approach

[0045] A test method for the DRAM stack package according to the first embodiment of the present invention will be described.

[0046] First, use Figure 1 ~ Figure 4 A test method of a functional test for testing the connection (connection format) of address, command and data signal lines between the interface chip in the DRAM stack package and the DRAM as the first embodiment of the present invention will be described.

[0047] figure 1 A schematic configuration of a test structure in which the DRAM stack package 3 is, for example, a four-layer stack package is shown. The DRAM stack package 3 of the present invention is constituted by mounting a plurality of stacked DRAMs 4 and an interface chip 2 for making the chips connected from the external terminals of the connection testing device 1 into one chip. Furthermore, the tester 1 is connected to the external terminals 51-56 for input and output of addresses, commands and data of the DRAM stack package (for example, 4-layer...

no. 2 Embodiment approach

[0088] Next, a test method of a DIMM (Dual in-line Memory Module) in which a plurality of DRAM stack packages are mounted on a substrate according to a second embodiment of the present invention will be described.

[0089] First, use Figure 5 with figure 2 The test method of the DIMM according to the second embodiment of the present invention will be described.

[0090] Figure 12 An embodiment of a test structure of a DIMM 100 in which a plurality of DRAM stack packages are mounted on a substrate is shown. The structure of the DIMM 100 according to the second embodiment of the present invention is that a plurality of substrates 101 are mounted with Figure 5 The DRAM stack package 3 configured in the first embodiment is shown. In the second embodiment of the test DIMM 100, the difference from the first embodiment is that the connection form when viewed from the test device 1 is as follows: Figure 12 As shown, addresses, commands, banks, clocks, and DQ control are comm...

no. 3 approach

[0099] use Figure 13 A test flow of a DRAM and a DIMM using a semiconductor test apparatus as a third embodiment of the present invention and a semiconductor manufacturing method will be described. The test procedure of DRAM and DIMM is: at first, carry out the probe inspection (S132) under the wafer state after preceding step procedure (S131) ​​finishes, here carry out salvage processing (1) (S133) to defective DRAM. After that, interface chip 2 and DRAM 4 are stacked (S134), packaged (S135), and screening inspection (1) and rescue treatment (2) are performed using the testing device of the present invention (S136, S137). Thereafter, package-on-package DIMM assembly (S138) is performed, and screening inspection (2) and salvage processing (3) are performed using the test device of the present invention (S139, S140). DRAM capacity is small, there are few inconsistent DRAMs in the screening inspection after packaging, and even if the inconsistent DRAMs are discarded as defecti...

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Abstract

The present invention relates to a DRAM stacked packages, a DIMM, a method for testing them, and a semiconductor manufacturing method. According to the present invention, there is provided a DRAM stacked package comprising: a plurality of stacked DRAMs; external terminals to which test equipment is connected, said external terminals being used to input / output at least address, command, and data; and an interface chip provided between said plurality of stacked DRAMs and said external terminals. The plurality of DRAMs and the interface chip are implemented on a package. The interface chip comprises: a test circuit including: an algorithmic pattern generator for generating a test pattern used to test the plurality of DRAMs; applying circuits for applying said generated test pattern to the plurality of DRAMs; and a comparator for comparing each response signal received from the plurality of DRAMs with an expected value for judgment.

Description

technical field [0001] The present invention relates to DRAM stack package, DIMM and its test method and semiconductor manufacturing method. Background technique [0002] As a conventional test method for semiconductor devices, JP-A-2001-35188 (Patent Document 1) is known. In this patent document 1, the following content is recorded: at least 3 or more than 3 DRAMs that can be independently accessed are installed on the chip, and at least one of the 3 or more than 3 DRAMs is stored with other DRAMs. In the test method of semiconductor devices with different capacities, when each DRAM is tested by inputting an independent test address signal to each DRAM, the DRAM with the longest test time is excluded, and at least 2 DRAMs among the other DRAMs are tested. In the serial test, the above-mentioned DRAM with the longest test time is tested in parallel with the serial test. [0003] As memory I / O speeds up, the number of memories that can be connected to data transmission line...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C7/10G01R31/28G11C11/401G11C29/12G11C29/56
CPCG11C5/04G11C29/48G11C2029/2602G11C2029/5602G11C11/4093G11C29/00
Inventor 其田佑次菊池修司平野克典安生一郎片桐光昭
Owner HITACHI LTD
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