Memory bus termination

[0029] The following description describes the technology used for the terminal memory bus. In the following description, many specific details such as logic implementation, operation code, method of determining operands, implementation of resource division/sharing/replication, types and relationships of system components, and logical partition/integration options are explained , In order to provide a more comprehensive understanding of the present invention. However, those skilled in the art will recognize that the present invention can be implemented without using these specific details. In order not to obscure the present invention, in other examples, the control structure, gate-level circuits, and all software instruction sequences do not appear in the details. Those of ordinary skill in the art will be able to implement appropriate functions based on the included instructions without undue experimentation.

[0030] The “one embodiment”, “one embodiment”, “an example embodiment” and so on mentioned in the specification indicate that the described embodiment may include a specific component, structure or feature, but each embodiment need not be all Including the specific component, structure or feature. Moreover, such phrases do not necessarily refer to the same embodiment. In addition, when a specific component, structure, or feature is described in combination with an embodiment, it is considered to fall within the knowledge of those skilled in the art, so that it can be combined with other embodiments to realize such component, structure, or Features, regardless of whether these embodiments are explicitly described.

[0031] The embodiments of the present invention can be implemented by hardware, firmware, software, or any combination thereof. The embodiments of the present invention can also be implemented by storing instructions on a machine-readable medium, and these instructions can be read and executed by one or more processors. A machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (eg, a computing device). For example, machine-readable media may include read-only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; flash memory devices; electrical, optical, acoustic, or other forms of propagated signals (such as carrier waves, infrared Signal, digital signal, etc.) and others.

[0032] figure 1 An example embodiment of the computing device 100 is shown. The computing device 100 may include one or more processors 102 connected to a chipset 104 via a processor bus 106. The chipset 104 may include one or more integrated circuit components or chips to connect the processor 102 with the system memory 108 and other devices 110 (such as a mouse, keyboard, video controller, hard disk, floppy disk, firmware, etc.). The chipset 104 may include a processor bus interface 112 for accessing the processor bus 106, a storage controller 114 for accessing the system memory 108, and one or more device interfaces 116 for accessing the device 110. In other embodiments, the processor 102 may include all or part of the storage controller 114. The processor bus interface 112 may decode the processor bus transaction issued by the processor 102, and may generate a processor bus transaction representing the storage controller 114 and/or the device interface 116. The device interface 116 provides an interface for communicating with the device 110. The device 110 is connected to the chipset 104 via the device bus 118. The device bus 118 is, for example, a Peripheral Component Interconnect (PCI) bus, an accelerated graphics interface (AGP) bus, or a universal serial bus ( USB), few pin type (LPC) bus and/or other I/O bus.

[0033] The memory controller 114 may include one or more memory input/output (I/O) buffers 120 to send data to and receive data from the system memory 108 via the memory bus 122 in the memory bus 124. The system memory 108 can be implemented using different volatile and non-volatile memory technologies, such as, for example, flash memory, static memory (SRAM), dynamic memory (DRAM), double data rate memory (DDR), and RAMBUS Memory. The memory controller 114 may further include a write latch 126 and a read latch 128. The write latch 126 stores data to be transferred to the system memory 108 via the memory I/O buffer 120, and the read latch 128 stores data via the memory The I/O buffer 120 receives data from the system memory 108. The storage controller 114 may further include a control logic 130 to control data transfer between the latches 126 and 128 and the processor bus interface 112. The control logic 130 may further calibrate the memory I/O buffer 120, and may control the transfer between the latches 126, 128 and the system memory 108 via the memory I/O buffer 120.

[0034] Reference now figure 2 , An embodiment of the storage controller 114 is shown. As mentioned, the memory I/O buffer 120 of the memory controller 114 includes an input buffer 200, and the input buffer 200 includes a receiver 202 and an output buffer 204. The output buffer 204 and the receiver 202 are connected to a memory bus terminal 206. The memory bus terminal 206 is, for example, a memory bus pad, contact, or pin for transferring data to and from the system memory 108. The input buffer 200 in one embodiment uses the output buffer 204 to terminate the terminal 206 during memory read and/or idle states so that the receiver 202 can accurately receive a data signal from the terminal 206 and provide the received data. Give the read latch 128.

[0035] In one embodiment, the output buffer 204 includes a programmable pull-up impedance device 208 connected between the high voltage source VHIGH (for example, 1.5 volts) and the terminal 206. The output buffer 204 further includes a programmable pull-down impedance device 210 that is connected between the terminal 206 and a low voltage source (for example, ground). The pull-up device 208 includes an impedance control input PUIMP to receive the pull-up control signal, and the pull-down device 210 includes an impedance control input PDIMP to receive the pull-down control signal. In one embodiment, the impedance control inputs PUIMP and PDIMP each include multiple input lines to receive multi-bit control signals. In another embodiment, the impedance control inputs PUIMP and PDIMP each include a single input line to receive control signals with only two states. In another embodiment, the impedance control inputs PUIMP and PDIMP each include a single input line to receive the encoded or serially transmitted control signal.

[0036] The pull-up device 208 disconnects the high voltage source VHIGH from the terminal 206 to respond to the disconnection command of the pull-up control signal. In one embodiment, the pull-up device 208 cuts off the high voltage source VHIGH and the terminal 206 by forming a very high impedance between the high voltage source VHIGH and the terminal 206. In addition, the pull-up device 208 pulls the terminal 206 to the voltage of the high voltage source VHIGH in response to the activation command of the pull-up control signal. In one embodiment, the pull-up device 208 pulls up the terminal to the high voltage source VHIGH by forming a pull-up impedance between the high voltage source VHIGH and the terminal 206, and the terminal 206 has an amplitude controlled by the pull-up control signal. .

[0037] Similarly, the pull-down device 210 disconnects the low voltage source VLOW from the terminal 206 in response to the disconnection command of the pull-down control signal. In one embodiment, the pull-down device 210 cuts off the low-voltage source VLOW and the terminal 206 by forming an extremely high impedance between the low-voltage source VLOW and the terminal 206. In addition, the pull-down device 210 pulls the terminal 206 to the voltage of the low voltage source VLOW in response to the activation command of the pull-down control signal. In one embodiment, the pull-down device 210 pulls the terminal 206 to the low-voltage source VLOW by forming a pull-down impedance between the low-voltage source VLOW and the terminal 206, and the terminal 206 has an amplitude controlled by the pull-down control signal.

[0038] The memory controller 114 further includes an impedance controller 212 to control the impedance of the pull-up and pull-down devices 208 and 210. In one embodiment, the impedance logic 212 includes a data input D to receive a data signal that represents data to be written to the system memory 108, and a write input W/RI to receive a write signal or a read signal. Indicates whether the memory I/O buffer 120 needs to be configured for memory write or memory read. The impedance controller 212 may also include a write impedance input WIMP to receive a write control signal that indicates the programmable impedance of the pull-up and pull-down devices 208, 210 during memory writing. The impedance control logic 212 may also include a read impedance input RIMP to receive a read control signal that indicates the programmable impedance of the pull-up and pull-down devices 208, 210 during a memory read or idle state.

[0039] The impedance controller 212 may further include a pull-up control output PUCTL connected to the impedance control input PUIMP of the pull-up device 208. In one embodiment, the impedance controller 212 generates a pull-up control signal on the pull-up control output PUCTL. The pull-up control signal depends on its data input D, write input W/RI, write impedance input WIMP, and read impedance. Input the data signal, write signal, write control signal and read control signal received by RIMP. The impedance controller 212 may also include a pull-down control output PDCTL connected to the impedance control input PDIMP of the pull-down device 210. In one embodiment, the impedance controller 212 generates a pull-down control signal on the pull-down control output PDCTL. The pull-down control signal depends on the data input D, write input W/RI, write impedance input WIMP, and read impedance input RIMP. Data signal, write signal, write control signal and read control signal.

[0040] The control logic 130 of the memory controller 114 may include an impedance calibration element 214 to provide the impedance controller 212 with a read control signal and a write control signal via its read control output RCTL and its write control output WCTL. The impedance calibration element 214 may include one or more environmental inputs EIN to receive one or more environmental parameters, and the impedance calibration element 214 may adjust the read control signal and the write control signal through these environmental parameters. The impedance calibration element 214 can use different technologies to adjust the read control signal and the write control signal according to the environmental signal of the environmental input EIN. For example, in one embodiment, the impedance calibration element 214 may receive temperature signals, voltage signals, and/or silicon processing signals from sensors, configuration registers, or other devices, and may adjust the read and write control signals according to the received signals.

[0041] In another embodiment, the impedance calibration element 214 may receive a signal as a result of connecting the calibration resistor RCOMP and the reference voltage VREF to the environmental input EIN. The impedance calibration element 214 can obtain the pull-up calibration value and the pull-down calibration value by selectively turning on the transistor of the impedance calibration element 214 until a predetermined relationship between the calibration resistance RCOMP and the reference voltage VREF is obtained. Refer to the US 6347850 "Programmable Buffer Circuit" submitted on December 23, 1999 for the realization of the impedance calibration element 214, which is based on the effective resistance value of the calibration resistor RCOMP and the reference voltage VSWING To obtain the pull-up calibration value and pull-down calibration value. However, it should be recognized that other known calibration techniques can be used to compensate for process, voltage, and/or temperature changes.

[0042] The impedance calibration element 214 may further include a calibration table 216 of control values. According to the table, the impedance calibration element 214 may generate a write control signal and a read control signal. The impedance calibration element 214 can use the index value of the parameter signal from the environmental input EIN to index the calibration table 216 to receive control values ​​that describe process, voltage, and/or temperature changes. In one embodiment, the calibration table 216 contains a write pull-up value and a read pull-up value, which are indexed to the pull-up calibration value from the calibration resistor RCOMP and the voltage reference VREF. In addition, the calibration table 216 contains the pull-down value and the pull-down value, which are indexed to the pull-down calibration value from the calibration resistor RCOMP and the voltage reference VREF. It should be recognized that the control value can be indexed into other values ​​that account for process, voltage, and/or temperature changes.

[0043] As described, the memory controller 114 includes a single memory I/O buffer 120. However, in other embodiments, the memory controller 114 may include an independent memory I/O buffer 120 for each memory bus 122 or a group of memory buses 122. In addition, the memory controller 114 may include an independent impedance controller 212 and/or an independent impedance calibration element 214 for each memory I/O buffer 120. Such an embodiment can program the impedance of the memory I/O buffer 120 separately.

[0044] in image 3 In, one embodiment of the impedance controller 212 and the output buffer 204 is shown. As shown, the output buffer 204 may include a set of P-channel MOSFETs 300 arranged in parallel between the high voltage source VHIGH and the terminal 206, and a set of n-channel MOSFETs 302, which are arranged between the low voltage source VLOW and the terminal 206. 206 are arranged in parallel. When the pull-up device 208 is activated, the number and value of the turned-on p-channel MOSFET 300 determines the impedance formed between the high voltage source VHIGH and the terminal 206. Similarly, when the pull-down device 210 is activated, the number and value of the n-channel MOSFET 302 that are turned on determines the impedance formed between the low voltage source VLOW and the terminal 206. In one embodiment, the MOSFETs 300, 302 are sized in binary series to allow a wide range of impedance programming (e.g., between 25 and 500 ohms), and have a sufficient number to obtain a sufficiently small particle size (e.g., about 1.5 ohm). As described, the pull-up device 208 of the output buffer 204 includes four p-channel MOSFETs 300, and the pull-down device 210 includes four n-channel MOSFETs 302. However, in other embodiments, the pull-up device 208 and the pull-down device 210 may include other numbers of switching devices (for example, MOSFET, JFET, etc.). Moreover, in other embodiments, the pull-up device 208 may include fewer or more switching devices than the pull-down device 210.

[0045] As shown, the impedance controller 212 includes a pull-up multiplexer 304 and a pull-down multiplexer 306. The pull-up multiplexer 304 includes AND gates 308 and 310 and a NOR gate 312, and the pull-down multiplexer 306 includes AND gates 314, 316 and an OR gate 318. However, it should be appreciated that other embodiments may implement the impedance controller 212 in different ways. The pull-up multiplexer 304 generates a pull-up control signal that selectively turns on zero or more p-channel MOSFETs 300, and the pull-down multiplexer 306 generates a pull-down control signal that selectively turns on Pass zero or more n-channel MOSFET302. In one embodiment, the pull-up multiplexer 304 is based on the data signal of the data input D, the write signal of the write input W/RI, and the pull-up part WPU[0] of the write control signal received in the write impedance input WIMP. :3], and the pull-up part RPU[0:3] of the read control signal received in the read impedance input RIMP generates the pull-up control signal. Similarly, the pull-down multiplexer 306 is based on the data signal of the data input D, the write signal of the write input W/RI, the pull-down portion WPD[0:3] of the write control signal received in the write impedance input WIMP, and The pull-down part RPD[0:3] of the read control signal received in the read impedance input RIMP generates the pull-down control signal.

[0046] In one embodiment, the impedance controller 212 and the memory I/O buffer 120 operate in the write mode in response to the write input W/RI value being high. As can be seen, when the value of the data input D is low and the value of the write input W/RI is high, the output of each AND gate 308, 310 is low, so that the output of each NOR gate 312 is high. As a result of the high output of the NOR gate 312, each p-channel MOSFET 300 is turned off and the pull-up device 208 is deactivated. In addition, when the value of the data input D is low and the value of the write input is high, the output of each AND gate 314 and therefore the output of each OR gate 318 depends on the corresponding bit of the writing part WPD[0:3] status. In particular, if a bit of the write-down part WPD[0:3] is high, the corresponding output of the OR gate 318 is high, so that the pull-down device 210 is activated by turning on the corresponding n-channel MOSFET 302. Conversely, if a certain bit of the write-down part WPD[0:3] is low, the corresponding output of the OR gate 318 is low, thereby turning off the corresponding n-channel MOSFET 302.

[0047] Similarly, when the value of the data input D is high and the value of the write input W/RI is high, the output of each AND gate 314, 316 is low, thus making the output of each OR gate 318 low. As a result of the low output of the OR gate 318, each n-channel MOSFET 300 is turned off and the pull-down device 210 is disabled. In addition, when the value of the data input D is high and the value of the write input is high, the output of each AND gate 308 and therefore the output of each NOR gate 312 depends on the write pull-up part WPD[0:3] corresponding to The state of the bit. In particular, if a bit of the write-up WPD[0:3] is high, the corresponding output of the NOR gate 318 is low, so that the pull-up device 208 is activated by turning on the corresponding p-channel MOSFET 300. Conversely, if a certain bit of the write-up WPD[0:3] is low, the corresponding output of the NOR gate 312 is high, thereby turning off the corresponding p-channel MOSFET 300.

[0048] In one embodiment, the impedance controller 212 and the memory I/O buffer 120 operate in a read mode and/or an idle mode in response to the write input W/RI value being low. As can be seen, when the value of the write input W/RI is low, regardless of the value of the data input D, the output of each AND gate 310 and therefore the output of each NOR gate 312 depends on the read pull-up part RPU[0 :3] The status of the corresponding bit. In particular, if a bit of the read pull-up portion RPU[0:3] is high, the corresponding output of the NOR gate 312 is low, so that the pull-up device 208 is activated by turning on the corresponding p-channel MOSFET 300. Conversely, if a bit of the read pull-up part RPU[0:3] is low, the corresponding output of the NOR gate 312 is high, thereby turning off the corresponding p-channel MOSFET 300.

[0049] Similarly, when the value of the write input W/RI is low, regardless of the value of the data input D, the output of each AND gate 316 and therefore the output of each OR gate 318 depends on the corresponding bit of the read pull-down portion RPD[0:3] status. In particular, if a certain bit of the read pull-down portion RPD[0:3] is high, the corresponding output of the OR gate 318 is high, so that the pull-down device 210 is activated by turning on the corresponding n-channel MOSFET 302. Conversely, if a bit of the read pull-down part RPD[0:3] is low, the corresponding output of the OR gate 318 is low, thereby turning off the corresponding n-channel MOSFET 302.

[0050] Reference now Figure 4 , The operation of an embodiment of the storage controller 114 is described. At block 400, the impedance calibration element 214 adjusts the write control signal and the read control signal to account for changes in process, voltage, and/or temperature. In one embodiment, the write control signal includes a write pull-up part WUP[0:3] and a write-down pull part WPD[0:3] to control the impedance of the pull-up device 208 and the pull-down device 210 respectively during memory write. Similarly, in one embodiment, the read control signal includes a read pull-up part RPU[0:3] and a read pull-down part RPD[0:3] to control the pull-up device during memory read and/or idle states, respectively 208 and pull-down device 210 impedance.

[0051] In block 402, the control logic 130 provides a write control signal to the write impedance input WIMP of the impedance controller 212, and the write control signal includes a write pull-up part WPU[0:3] and a write-down pull part WPD[0:3]. Similarly, at block 404, the control logic 130 provides a read control signal to the read impedance input RIMP of the impedance controller 212, the read control signal includes a read pull-up part RPU[0:3] and a read pull-down part RPD[0:3 ].

[0052] In block 406, the control logic 130 determines whether to perform a memory write based on the signal received from the processor bus interface 112 and the state of the memory bus 124. In response to the decision to perform the memory write, the control logic 130 in block 408 provides a high write signal to the write input W/RI of the impedance controller 212 to indicate the memory write. In turn, the control logic 130 in block 410 provides a low write signal to the write input W/RI of the impedance controller 212 to indicate the read and/or idle state of the memory, in response to the decision not to perform memory write.

[0053] The impedance controller 212 in block 412 either activates the pull-up device 208 or the pull-down device 210 to drive the data signal on the memory bus 122. In one embodiment, the impedance controller 212 responds to its data input D being high, and provides a pull-up control signal to the impedance control input PUIMP of the output buffer 204. The pull-up control signal activates the pull-up device 208, the The pull-up device 208 has an impedance specified by the write pull-up part WPU[0:3] of its write impedance input WIMP, and provides a pull-down control signal to the impedance control input PDIMP of the output buffer 204, and the pull-down control signal causes the The pull-down device 210 fails. Similarly, in one embodiment, the impedance controller 212 responds to its data input D being low by providing a pull-down control signal to the impedance control input PDIMP of the output buffer 204, which activates the pull-down device 210, The pull-down device 210 has an impedance specified by its write impedance input WIMP's write-down part WPD[0:3], and provides a pull-up control signal to the impedance control input PUIPP of the output buffer 204. The pull-up control signal causes the The pull-up device 210 fails.

[0054] The output buffer in block 414 drives the data signal on the system bus 122 via the terminal 206. In one embodiment, the output buffer 204 pulls the memory bus 122 to the high voltage source VHIGH via the programmable impedance of the pull-up device 208 to drive the high-level data signal on the memory bus 122 in response to the pull-up device 208 Is activated and the pull-down device 210 is deactivated. Similarly, the output buffer 204 pulls the memory bus 122 to the low voltage source VLOW via the programmable impedance of the pull-down device 210 to drive the low-level data signal on the memory bus 122 to pull up in response to the pull-down device 210 being activated. The device 208 is invalidated.

[0055] In response to deciding not to perform memory writing, the impedance controller 212 in block 416 activates and controls the impedance of the pull-up device 208 and the pull-down device 210 to terminate the memory bus 122 during the memory read and/or idle state. In one embodiment, the impedance controller 212 responds to its write input W/RI being low and provides a pull-up control signal to the impedance control input PUIPP of the output buffer 204, and the pull-up control signal activates the pull-up device 208, The pull-up device 208 has an impedance specified by the read pull-up part RPU[0:3] of its read impedance input RIMP. In addition, the impedance controller 212 responds to its write input W/RI being low, and provides a pull-down control signal to the impedance control input PDIMP of the output buffer 204. The pull-down control signal activates the pull-down device 210, which has a The read impedance input the impedance specified by RPD[0:3] in the read pull-down part of RIMP.

[0056] In block 418, the output buffer 204 terminates the memory bus 122 according to the received pull-up and pull-down control signals. In one embodiment, the output buffer 204 pulls the memory bus 122 to the high voltage source VHIGH via the programmable impedance of the pull-up device 208, and pulls the memory bus 122 to the low voltage source VLOW via the programmable impedance of the pull-down device 210. Therefore, the programmable impedances of the pull-up and pull-down devices 208, 210 combine to terminate the memory bus 122. For example, the pull-up device 208 can establish a 400 ohm impedance between the high voltage source VHIGH and the terminal 206, and the pull-down device 210 can establish a 400 ohm impedance between the low voltage source VLOW and the terminal 206, thereby connecting the terminal 206 and the voltage A 200 ohm read termination impedance is established between the sources VHIGH and VLOW.

[0057] Although certain features of the present invention have been described with reference to example embodiments, these descriptions should not be construed as limiting the present invention. Various modifications of the exemplary embodiments and other embodiments of the present invention are obvious to those skilled in the art, and are deemed to fall within the spirit and scope of the present invention.