Memory bus termination

Abstract

Methods, apparatus and machine-readable medium are described to terminate a memory bus line. In some embodiments, the memory bus line is terminated with one or more transistors of an output buffer that are used to drive the memory bus line during a memory write.

Description

technical field [0001] The present invention relates to a computing device and its memory controller and control method. Background technique [0002] Data transfer rates between system memory and memory controllers continue to increase. To improve signal integrity at higher transfer rates, memory devices and memory controllers include termination resistors that match the impedance of the memory bus to reduce signal reflections on the memory bus. Conventional memory controllers include separate termination resistors that are connected to the memory bus during the read and / or idle states of the memory bus. Additionally, these memory controllers contain additional logic to maintain constant impedance over process, voltage, and temperature. These memory controllers further include circuitry to disconnect the termination resistors from the memory bus during memory writes. These additional termination resistors, logic, and circuitry associated with terminating the memory bus c...

AI Technical Summary

Problems solved by technology

These additional termination resistors, logic and circuitry associated with terminating the memory bus consume additional footprint

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