Plasma display panel apparatus and method for driving the same
A display panel and plasma technology, applied in the direction of static indicators, instruments, etc., can solve the problems that it is difficult to ensure the design margin of auxiliary elimination pulse, unresolved abnormal initialization discharge, difficult to set the amplitude, etc., to achieve good image display performance, supervision Maintain discharge normally and solve the effect of discharge delay
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Embodiment approach 1
[0073] (Overall configuration of PDP device)
[0074] FIG. 1 is a partial perspective view showing a configuration example of a PDP. The PDP 1 shown in this figure is generally the same as the conventional configuration described above, and redundant descriptions are appropriately omitted. The configurations of the PDP and its driving device are substantially the same in each of the embodiments described later.
[0075] The PDP 1 is configured such that a front substrate (front panel: front panel) 2 and a rear substrate (back panel: rear panel) 3 made of panel glass are arranged to face each other, and a discharge space is formed therebetween.
[0076] On a single main surface of the front substrate 2, a plurality of scan electrodes SCN1-SCNn and SUS1-SUSn constituting a display electrode pair are arranged in parallel to each other. Dielectric material layer 6 and protective layer 7 are sequentially stacked so as to cover the plurality of scan electrodes SCN1 to SCNn and SUS...
Embodiment approach 2
[0166] 8 is a diagram showing driving waveforms in an initialization period of all cells of the PDP according to Embodiment 2 of the present invention.
[0167] The second embodiment is characterized in that the driving waveforms shown in FIG. 4 are applied to the electrodes representing the PDP during the initialization of all cells, as shown in FIG. 8 . Sustain electrodes SUS1 to SUSn are applied with an excess wall voltage elimination period in which a vertical potential change waveform (voltage change pulse) is applied.
[0168] The operations and subfield configurations of the first half and the second half of the initialization period in Embodiment 2 are the same as those in Embodiment 1, so descriptions thereof are omitted, and an excess wall voltage erasing period different from Embodiment 1 will be described.
[0169] In FIG. 8( a ), after the first half of the initialization period ends, after applying a voltage Vg (V) to the scan electrodes SCN1 to SCNn, the dischar...
Embodiment approach 3
[0178] 9 is a diagram showing driving waveforms in an initialization period of all cells of the PDP according to Embodiment 3 of the present invention.
[0179] The third embodiment is characterized in that the driving waveforms shown in FIG. 4 applied to the electrodes of a typical PDP are set between the first half and the second half of the entire cell initialization period as shown in FIG. The excess wall voltage elimination period in which a vertical potential change waveform is applied to data electrodes D1 to Dm.
[0180] The operations and subfield configurations of the first half and the second half of the initialization period in the third embodiment are the same as those in the first embodiment, so descriptions thereof are omitted, and the excess wall voltage erasing period, which is different from that in the first embodiment, will be described.
[0181] In FIG. 9(a), after the first half of the initialization is completed, and Vg (V) is applied to the scan electro...
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