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Multiple clock system integrative circuit plane layout method

An integrated circuit and plane layout technology, applied in the direction of electrical digital data processing, special data processing applications, instruments, etc., can solve the problem of not considering the connection relationship of the clock area

Inactive Publication Date: 2007-10-17
FUDAN UNIV
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AI Technical Summary

Problems solved by technology

In [2], it is proposed to consider the layout of the clock region, and realize that the modules of the same clock region are adjacent to each other in the final layout, but the connection relationship between different clock regions is not considered, and this factor is very important for the final clock region. Tree generation and line length optimization have practical implications

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  • Multiple clock system integrative circuit plane layout method
  • Multiple clock system integrative circuit plane layout method
  • Multiple clock system integrative circuit plane layout method

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Embodiment Construction

[0041] The method of the present invention is further described below through two standard test examples.

[0042] (1) Read layout standard test cases, store the area, length and width, type, connection and clock information of each module;

[0043] (2) Select the initial sequence pair: Since the simulated annealing optimization has nothing to do with the initial solution, the serial numbers of the modules can be taken in clock order to form a sequence pair, which can satisfy the constraint condition (1). At the same time, in the following simulated annealing process, the operation of the sequence pair Keep the serial numbers corresponding to the same clock module always adjacent;

[0044] (3) First, the simulated annealing method is used to optimize to find the optimal solution of the objective function. This process is mainly optimized for the constraints of the connection relationship between different clock regions: set the initial annealing temperature to 1, and the termi...

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Abstract

The invention belongs to the technical field of integrated circuit computer-aided design, specificly relates to a method of layout for the integrated circuit plane of multifunction clock system. The invention, based on the representation of sequence pairs and the simulating annealing algorithm as well as the linear programming algorithm, provides a method of layout for plane under thinking about the interconnecting relation between areas of multifunction clock. The invention, while keeping the neighborhood of the same clock modules, can carry out the neighborhood in the final layout for the modules which are interconnected between different clock areas, and much more approach the request of practical integrated circuit, and can be used in the computer-aided design of integrated circuit.

Description

technical field [0001] The invention belongs to the technical field of computer-aided design of integrated circuits, and in particular relates to a layout planning method considering new constraint factors, in particular to a plane layout layout planning method considering the connection relationship between different clock regions for a multi-clock system. Background technique [0002] With the continuous expansion of the scale of integrated circuits, the layout of integrated circuits becomes more and more complex, so the research on floorplanning algorithms of integrated circuits has received extensive attention in recent years. On the basis of considering the main area and line length optimization, more and more practical factors are taken into account, which increases the practicability of the layout algorithm. In [2], it is proposed to consider the layout of the clock region, and realize that the modules of the same clock region are adjacent to each other in the final l...

Claims

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Application Information

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IPC IPC(8): G06F17/50
Inventor 王琳凯周晓方
Owner FUDAN UNIV
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