Semiconductor wafer including semiconductor chips divided by scribe line and process-monitor electrode pads formed on scribe line
A technology for monitoring electrodes and semiconductors, used in semiconductor/solid-state device testing/measurement, semiconductor device, semiconductor/solid-state device manufacturing, etc., and can solve problems such as increased manufacturing costs
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no. 1 example
[0091] 1A and 1B are schematic diagrams for describing a semiconductor wafer 1 according to an embodiment of the present invention. More specifically, FIG. 1A is a plan view showing the vicinity of a scribe line of the semiconductor wafer 1 , and FIG. 1B is a cross-sectional view taken along line A-A of FIG. 1A . FIG. 2 is a plan view showing the general structure of the semiconductor wafer 1 according to the embodiment of the present invention. 3A and 3B are schematic diagrams for describing a portion of a process monitoring apparatus placed on a scribe line according to an embodiment of the present invention. More specifically, FIG. 3A is a plan view showing a part of the process monitoring device, and FIG. 3B is a cross-sectional view taken along line B-B of FIG. 3A . The semiconductor wafer 1 according to the embodiment of the present invention has a three-layer metal wiring structure.
[0092] As shown in FIG. 2 , the semiconductor wafer 1 has a plurality of semiconduct...
no. 2 example
[0138] 16A and 16B are schematic diagrams illustrating a semiconductor wafer 101 according to an embodiment of the present invention. More specifically, FIG. 16A is a plan view showing the vicinity of the scribe line 105 of the semiconductor wafer 101, and FIG. 16B is a cross-sectional view taken along line A-A of FIG. 16A. FIG. 17 is a plan view showing the general structure of a semiconductor wafer 101 according to an embodiment of the present invention. 18A and 18B are schematic diagrams for describing a process monitoring apparatus placed on a scribe line according to an embodiment of the present invention. More specifically, FIG. 18A is a plan view showing a part of the process monitoring device, and FIG. 18B is a cross-sectional view taken along line B-B of FIG. 18A . The semiconductor wafer 101 according to the embodiment of the present invention has a three-layer metal wiring layer structure.
[0139] As shown in FIG. 17 , the semiconductor wafer 101 has a plurality ...
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