Receiver and receiving method

A receiving device and receiving method technology, applied to the shaping network, electrical components, transmission system, etc. in the transmitter/receiver, can solve the problems of processing time variation, complex control circuit, large circuit scale, etc., and reduce the circuit scale Effect

Inactive Publication Date: 2008-03-05
NEC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0011] The first problem is that since the chip repetition synthesizer 81 needs a memory of a size corresponding to the maximum value of Q, the circuit scale is large.
The second problem is: if the chip repetition unit Q is variable, it is necessary to control the actions of the chip repetition synthesizer 81, FFT circuit 82, IFFT circuit 84, etc. according to Q, so the control circuit becomes complicated
[0012] The third problem is that if a part of the FFT circuit is used for processing according to the chip repetition unit Q, the processing time varies according to the chip repetition unit Q.

Method used

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Embodiment Construction

[0036] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a receiving device according to a first embodiment of the present invention. The receiving device 10 includes an FFT circuit 11 , a weight multiplier 12 , an IFFT circuit 13 and a control circuit 14 . Similar to the conventional receiver shown in FIG. 8, this receiver 10 is configured as a receiver for receiving a signal transmitted by chip repetition by frequency domain equalization using the Code Division Multiple Access (CDMA) method. FIG. 2 shows the received signal as a time diagram. The receiver 10 sets the oversampling rate as M (M is a power of 2), sets the number of chip repetitions as R (R is a power of 2), and sets the chip repetition unit as Q (Q is a power of 2). Multiplication), for one group, the signal of M×Q chips is repeated R times for reception.

[0037] The FFT circuit 11 performs M×R...

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Abstract

An FFT circuit (11) performs fast Fourier transform of a receiving signal at MRQ points, where M is the over sampling rate, Q is the chip repetition unit, and R is the chip repetition rate of the receiving signal. A weight multiplier (12) multiplies the frequency component having a frequency component number equal to integer times of R by a weighting factor for equalizing transmission line out of MRQ frequency components outputted from a fast Fourier transform circuit, and multiplies other frequency components by 0. A fast inverse Fourier transform circuit (13) receives the output from the weight multiplier (12) and performs fast inverse Fourier transform of the frequency component having a frequency component number equal to integer times of R.

Description

technical field [0001] The present invention relates to a receiving device and method, and more specifically, to receiving and using chip repetition (chip repetition) through frequency domain equalization in a transmission system that utilizes code division multiple access (CDMA) to transmit and receive signals. A receiving device and method for a signal sent by repetition). Background technique [0002] In recent years, communication of the CDMA system has been attracting attention as a communication method. As a technology related to CDMA communication, there is, for example, the technology described in JP-A-2004-297756. In this technology, at the transmitting end, the spread chip sequence is transmitted only a certain number of times in units of a certain number of chips. This situation is shown in FIG. 7 . In this example, the spread chip sequence is repeated R times for every Q chip. The repeated chip sequence is synthesized at the receiving end to restore the sprea...

Claims

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Application Information

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IPC IPC(8): H04B1/707H04B1/712H04L25/03
Inventor 望月孝志
Owner NEC CORP
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