Quasi-circulation low density parity code encoder and check bit generating method

Abstract

The invention discloses a quasi-cycle low density parity checking code encoder and the parity bit generating method and consists of a serial / parallel switch unit, an encoding matrix storage unit, an information bit cache unit, a core encoding unit and a serial / parallel switch unit; the method consists of: the information bit and the encoding matrix bit that is parallel input into the set width; the parallel parity bit is obtained by calculating the input parallel information and the parallel encoding matrix. The invention applies the parallel input of the information bit, the parity bit generating method of the parallel output of the parity bit into the quasi-cycle low density parity checking encoding to improve the encoding speed, save encoding source and is easy to meet half way between the encoding sources and the encoding speed.

Description

technical field [0001] The invention relates to the technical field of digital information, in particular to a quasi-cyclic Low Density Parity Check (Quasi-cyclic Low Density Parity Check, QC-LDPC) code encoder and a check bit generating method. Background technique [0002] In recent years, low density parity check (Low Density Parity Check, LDPC) codes have received extensive attention due to their excellent performance and structure that can be decoded in parallel (facilitating high-speed decoding). [0003] LDPC codes were first proposed by Gallager, see (R.G.Gallager, Low-Density Parity-Check Codes.Cambridge, MA: MIT.Press, 1963), with the in-depth research on Turbo codes, D.J.C.Mackay, M.Neal and N. Wiberg et al. re-researched LDPC codes, see (Mackay D J C. Good Error Correcting Codes Based on Very Sparse Matrices. IEEE Trans on Information Theory, 1999, 45(2): 399-431.) found that it is the same as Turbo codes It can approach the Shannon limit very well, and the cost...

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Problems solved by technology

[0021] 1) To a certain extent, the encoding speed is limited;

[0022] 2) The SIPO solution requires a high parallel output width of the coding matrix, high requirements on registers, and the maximum working speed is limited when implemented with FPGA (Field Programmable Gate Array, Field Programmable Gate Array);

[0023] 3) The PISO scheme requires information bits to be input in parallel at the same time, which is difficult to implement in practice, because for LDPC codes, the code length and information bits are often very long (thousands or even tens of thousands), and the maximum working speed is also affected by FPGA implementation. limit

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