Memory body and low offset limitation bias circuit thereof

Abstract

The invention relates to a memory and a low deviation value limiting bias circuit of the memory. The memory of the invention comprises a plurality of memory element array sections and a low deviation value limiting bias circuit, wherein each memory element array section is provided with a plurality of memory elements and the low deviation value limiting bias circuit comprises a constant voltage generator and a limiting bias circuit modulator. The low deviation value limiting bias circuit of the invention decreases the variable of a pole voltage (Vd) provided to the memory units in the memory unit array sections via a feedback mechanism composed by the limiting bias circuit modulator and the constant voltage generator so that no matter the memory is reading, writing or clearing, the accuracy can be improved.

Description

technical field [0001] The invention relates to a low offset limiting bias circuit of a memory, in particular to a low offset limiting bias circuit of a memory with multi-level memory cells. Background technique [0002] With today's memory (memory, storage medium, memory, memory, etc., hereinafter referred to as memory) types, such as flash memory (flash memory), dynamic random access memory (dynamic random access memory, DRAM) and Static random access memory (static random access memory, SRAM)... etc., which read (read), write (write) or clear (erase) data (data is data, hereinafter referred to as data ) accuracy has become one of the main indicators for manufacturers to develop memory products, and it is even more critical to enhance the competitiveness of memory products. [0003] As we all know, there are multiple memory cell array areas in the memory, and each memory cell array area has multiple memory cells, which can be multilevel memory cells. . see figure 1 As ...

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Problems solved by technology

[0014] Another object of the present invention is to overcome the defects existing in the existing memory and provide a memory with a new structure. The technical problem to be solved is to make it use the above-mentioned low offset limiting bias circuit of the present invention, In this way, not only the advantages of the low offset limiting bias circuit of the present invention can be achieved, but also the power consumption of the memory can be reduced at the same time, and in terms of chip design, the area occupied by it is relatively small, so it can reduce production costs

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