Signal amplifier of deep submicron dynamic memory

Abstract

The invention relates to a signal amplification circuit of a deep sub-micron dynamic memory, which comprises a memory cell and a sensitive amplification circuit of a dynamic memory, wherein the memory cell is composed of two capacitors and two transistors; the sensitive amplification circuit includes a cross-coupling amplification circuit, a bit line charging circuit and a switch circuit to construct a VCC dual-cell FRAM sensitive amplification circuit, a VCC2 dual-cell DRAM sensitive amplification circuit and a GND dual-cell DRAM sensitive amplification circuit; and the sensitive amplification circuit is connected with the source of the transistors of the memory cell to achieve high stability and high interference resistance.

Description

technical field [0001] The invention relates to an integrated circuit amplifier, in particular to a signal amplifying circuit for deep submicron dynamic memory. Background technique [0002] 1. Characteristics of silicon oxynitride SiON gate dielectric [0003] As the size of the field effect transistor MOSFET continues to shrink, in order to maintain good controllability of the drain current, it is necessary to reduce the thickness of the gate dielectric. In the CMOS process below 100 nm, the thickness of the gate oxide layer is already below 2 nm. As dimensions continue to shrink, gate leakage and reliability issues such as boron penetration of the gate electrode become a pressing issue. [0004] When the process size is below 180nm, the industry no longer uses pure SiO2 as the gate insulator, but uses low-doped oxynitride formed by thermal nitridation of the oxide as the gate insulator to prevent P+ multi-gate Boron penetration. Pure SiO 2 The dielectric constant k v...

AI Technical Summary

Problems solved by technology

After entering the deep submicron, the dynamic memory is faced with the operation voltage V CC The great challenge of reducing

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