Memory device detecting method
A detection method and memory technology, applied in static memory, instruments, etc., can solve problems such as virtual welding, adhesion, and complex address line detection process, and achieve the effect of improving detection efficiency and accurate detection results.
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[0075] Example 1
[0076] The first stage, reading and writing testing:
[0077] 1. HDDR is 0X0000000. Because the odd address of the memory cannot be read or written, EDDR is 0X1FFFFFE; for easy detection and calculation, set TD1 to "all 0", that is, 0X0000, and TD2 to "all 1", that is, 0XFFFF.
[0078] TD1 and TD2 can be interchanged, which does not affect the implementation of the present invention. The reason why TD1 and TD2 are set to "all 0" and "all 1" is to facilitate the setting of TDG1 and TDG2 in the second and third stages;
[0079] 2. Write TD1 to HDDR, read back and compare. If the result is correct, it means that each data line is set to low level '0' and it can be normal, which can eliminate the problem of the data line being constantly high level '1', and then , Go to the next step; if the result is not correct, it means that there is a problem in the reading and writing of the HDDR or the address line or the data line, stop the detection and report the problem;
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Example Embodiment
[0131] Example 2
[0132] The difference between this embodiment and embodiment 1 is: in the second and third stages of embodiment 1, if a data line or address line is found to be faulty, the fault is recorded and the detection is continued. In this embodiment, in the second stage and the third stage, as soon as the data line or the address line is found to be faulty, the detection is stopped, the problem is reported, and after the fault is eliminated, the memory detection is restarted. The detection procedures of the second stage and the third stage of this embodiment are as follows: Figure 5 with Figure 6 Shown.
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