Wafer level image sensor package with die receiving cavity and method of the same
A technology of image sensor and crystal grain, which is used in electric solid state devices, semiconductor devices, radiation control devices, etc.
Inactive Publication Date: 2008-08-20
ADVANCED CHIP ENG TECH INC
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There are also a plurality of conductive bumps coupled to the terminal pads
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[0037] The present invention will be described in detail with preferred embodiments and viewpoints, and such descriptions are to explain the structure and procedures of the present invention, and are only used for illustration and not for limiting the patent scope of the present invention. Therefore, in addition to the preferred embodiment in the description, the present invention can also be widely practiced in other embodiments, and the scope of the present invention is only limited by the accompanying claims.
[0038] The invention discloses a wafer-level packaging structure, which adopts a substrate, and the interior of the substrate has a pre-formed through hole structure and a chip containing hole. A photosensitive layer material is coated on the die and the preformed substrate. The material of the photosensitive layer is preferably elastic material.
[0039] FIG. 1 depicts a cross-sectional view of a fan out type wafer level package (FO-WLP, fan out type wafer level pa...
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Abstract
The present invention provides a packaging structure, which includes a substrate; a die containing hole is formed on the upper surface of the substrate, and a through-hole structure passes through it; a terminal pad is formed under the through-hole structure, and the substrate is combined A conductive wiring is formed on the lower surface of the substrate; a die is disposed in the die receiving hole in an adhesive manner, and a dielectric layer is formed on the die and the substrate; a redistribution metal layer (RDL) is formed on the The dielectric layer is coupled to the grain and the through hole structure; a plurality of conductive bumps are coupled to the terminal pad; an opening is formed on the dielectric layer and the upper protection layer and exposes the micromirror area of the image sensor grain. A protective layer (film) with water and oil repellent properties is coated on the micromirror area to prevent the area from being polluted by foreign particles. In addition, a transparent covering layer capable of filtering infrared rays may be formed on the micromirror area to protect the micromirror area.
Description
technical field [0001] The present invention relates to a wafer level package (WLP, wafer level package) structure, in particular to a carrier with a die receiving hole, which can accommodate the die of an image sensor in the wafer level package. Background technique [0002] In the field of semiconductor devices, the density of devices is continuously increasing, while the size of devices is also continuously shrinking. In order to cope with the above situation, the industry has higher and higher requirements for packaging and interconnection technology required for such high-density components. In a general flip-chip connection method, solder bumps are formed on the surface of the die in an array arrangement. It is formed by using a soldering composite material through a solder mask to produce the required solder bump pattern. The functions of chip packaging include distributing power and signals in the circuit, enhancing heat dissipation, providing protection and suppor...
Claims
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IPC IPC(8): H01L27/146H01L23/48H01L23/28H01L21/50H01L21/60H01L21/56
CPCH01L27/14618H01L27/14632H01L27/14687H01L31/0203H01L2224/24227H01L2924/01068H01L2924/01077H01L2924/01078H01L2924/01079H01L2924/09701H01L2924/10253H01L2924/15311H01L2924/00H01L23/04
Inventor 杨文焜张瑞贤林志伟周昭男
Owner ADVANCED CHIP ENG TECH INC