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Method for fabricating landing plug of semiconductor device

A technology for connecting plugs and semiconductors, which is applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, electric solid-state devices, etc., and can solve problems such as incomplete coverage of double-line word lines and difficulty in forming patterns.

Inactive Publication Date: 2010-09-08
SK HYNIX INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the I-mask cannot completely cover the two-line word line (gate) and spacers on both sides
Therefore it is difficult to form the desired pattern

Method used

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  • Method for fabricating landing plug of semiconductor device
  • Method for fabricating landing plug of semiconductor device
  • Method for fabricating landing plug of semiconductor device

Examples

Experimental program
Comparison scheme
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Embodiment Construction

[0015] 1a is a schematic view showing a process for forming a connection plug contact in a single exposure process using an I-type mask, and FIG. 1b is a cross-sectional view taken along line XX' of FIG. 1a.

[0016] Referring to FIGS. 1a and 1b , connection plug contacts are formed on a semiconductor substrate 100 (see FIG. 1b ) using an I-type mask 130 (see FIG. 1a ). Referring to FIG. 1 b , the interlayer insulating film between the gate 120 and the dummy gate 125 is once opened by using an I-type mask, so as to form contacts 140 in the word line intervals on the active region 110 defined by the isolation film 105 . That is, regions other than the I-type connection plug contact mask 130 are opened. However, when forming a pattern with a half-pitch smaller than 30 nm, it is difficult for the I-type mask 130 to cover the gate 120 (such as a double-lined word line) and spacers on both sides. Therefore, contacts are formed between the active region 110 and both ends of the act...

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PUM

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Abstract

A method of fabricating a landing plug of a semiconductor device includes performing a double patterning process to separately form a landing plug contact hole for a storage node and a landing plug contact hole for a bit line, thereby facilitating forming a device having a half pitch of 30 nm.

Description

technical field [0001] The present invention relates to a method of manufacturing a connection plug of a semiconductor device, and more particularly, to a method of manufacturing a connection plug of a semiconductor device including performing a double patterning process to obtain a device having a half-pitch of 30 nm. Background technique [0002] In the process of forming a semiconductor device, even with an immersion photolithography process, it is difficult to form a line / distance pattern. In order to improve the resolution of the photolithography process and increase the process margin, much research has been conducted on double patterning. Double patterning is the process of exposing and developing a photoresist-coated wafer using two masks. Double patterning is mainly used for complex patterns (ie not simple lines or contacts), or for exposing dense patterns and isolated patterns to increase process margin. The double patterning process involves exposing and etchi...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/768
CPCH01L21/31144H01L21/76816H10B12/0335H10B12/485
Inventor 金辰寿
Owner SK HYNIX INC