System and method for checking watchdog zero clearing signal

Abstract

The invention relates to a system and a method for detecting reset signals of watchdogs. The system comprises a maximum register, a minimum register, a statistic module and an alarm indication module, wherein the statistic module detects and acquires the pulse width of a watchdog signal, and compares the pulse width with a maximum pulse width value and a minimum pulse width value; the alarm indication module sends out an alarm indication signal under the circumstance that the pulse width is more than the maximum pulse width value or less than the minimum pulse width value. The method comprises the following steps of acquiring the pulse width in a watchdog reset signal, comparing the pulse width with the preset maximum pulse width value and the minimum pulse width, sending out the alarm indication signal under the circumstance that the pulse width is more than the maximum pulse width value or less than the minimum pulse width value. The method ensures that the system can detect the reset signals of all watchdogs, and greatly simplifies the operation of detecting the reset signals of all watchdogs.

Description

technical field [0001] The invention relates to a hardware watchdog signal detection technology, in particular to a system and method for detecting a watchdog clear signal. Background technique [0002] Watch Dog Timer (WDT for short) technology is the most common anti-jamming technology, and the watch dog is actually a timer counter that can be reset. When the timing counter is implemented with the external circuit of the central processing unit chip (Central Processing Unit, referred to as CPU), it is a hardware watchdog; when the timing counter is implemented with the internal timer or counter of the CPU chip, it is a software watchdog. [0003] The hardware watchdog has two ports: a reset terminal and a timing clear terminal. When the protected CPU system is running normally, the protected system will continuously send a changing level to the timing clear terminal, that is, the watchdog clear signal (WDI signal), to ensure that the watchdog timer is cleared in time, and...

AI Technical Summary

Problems solved by technology

[0006] The defect of detecting the WDI signal through the oscilloscope is: because the oscilloscope stores all the detected WDI signal pulses, and the storage space of the oscilloscope is very small, the oscilloscope can only perform segment detection and storage, resulting in inter-segment intervals, making the inter-segment interval WDI signal not detected

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