Method, system and device for reduced signal level support for memory devices

Abstract

Embodiments of the invention are generally directed to systems, methods, and apparatuses for reduced signal level support for memory devices. In some embodiments, a host includes one or more additional electrical contacts to provide a controllable voltage reference to a memory device. The host may also include driver circuitry to provide a driver signal to the memory device. In some embodiments, the driver signal is substantially symmetrical around the controllable voltage reference.

Description

technical field [0001] Embodiments of the present invention generally relate to the field of integrated circuits, and more particularly to systems, methods, and apparatus for reduced signal level support for memory devices. Background technique [0002] Relatively high speed interfaces such as double data rate (eg, DDR, DDR2, and DDR3, etc.) interfaces may include receivers that use a voltage reference (VREF). The input digital signal is compared to VREF to determine whether the input signal is a logic 0 or a logic 1. The voltage level of VREF acts as a trip point (or switch point). An input signal with a voltage level above the trip point is a logic level 1, and an input signal with a voltage level below the trip point is a logic level 0. [0003] A regulator that provides VREF also typically provides voltage to a memory device such as a dynamic random access memory device or DRAM. VREF is usually fixed at half the DRAM voltage. This configuration assumes that the DRAM ...

AI Technical Summary

Problems solved by technology

In this case, the signal level on the host side of the interface may not be supported by the receiver on the DRAM side of the interface

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