Expansion of a stacked register file using shadow registers

Abstract

One or more Shadow Register Files (SRF) are interposed between a Physical Register File (PRF) and a Backing Store (BS) in a shadow register file system. The SRFs comprise dual-port registers connected serially in a chain of arbitrary depth from the PRF. A Register Save Engine has random access to one port of the registers in the final SRF in the chain, and saves / restores data between the final SRF and the BS, e.g., RAM. As PRF registers are deallocated from calling procedures for use by called procedures, data are serially shifted from multi-port registers in the PRF through successive corresponding dual-port registers in SRFs, and are serially shifted back toward the multi-port registers as the PRF registers are reallocated to calling procedures. Since no procedure can access more than the number of registers in the PRF, the effective size of the PRF is increased, using less costly dual-port registers.

Description

technical field

[0001] The present invention relates generally to the field of processors, and in particular to using shadow registers to extend the effective size of a stack register file. Background technique

[0002] RISC processors are characterized by a relatively small instruction set, where each instruction performs a single instruction, such as an arithmetic, logical, or load / store operation. Arithmetic and logic instructions take their operands from one or more general purpose registers (GPRs) and write their results to the GPRs. GPRs are structured registers. That is, a GPR includes discrete memory locations that are clearly identified in the instruction set structure and are directly addressable by instructions.

[0003] GPRs are often implemented in hardware such as an array of high-speed multi-port registers, each of which has a word width (eg, 32 or 64 bits) defined by the instruction set. This physical register array is called the physical register file (Ph...

Examples

Embodiment Construction

[0021] figure 2A functional block diagram of processor 10 is depicted. The processor 10 executes the instructions in the instruction execution pipeline 12 according to the control logic 14 . Pipeline 12 may be a superscalar design, with multiple parallel pipelines, such as 12a and 12b. Each pipeline 12a, 12b includes various registers or latches 16 organized into stages, and one or more arithmetic logic units (ALUs) 18 . Pipelines 12a, 12b fetch instructions from an instruction cache (I-cache or I$) 20 where memory addressing and permissions are managed by an instruction-side translation lookaside buffer (ITLB) 22 .

[0022] Data is accessed from a data cache (D-cache or D$) 24 where memory addressing and permissions are managed by a main translation lookaside buffer (TLB) 26 . In various embodiments, ITLB 22 may include a replica of a portion of TLB 26 . Alternatively, ITLB 22 and TLB 26 may be integrated. Similarly, in various embodiments of processor 10, I-cache 20 and...

technical field

[0001] The present invention relates generally to the field of processors, and in particular to using shadow registers to extend the effective size of a stack register file. Background technique

[0002] RISC processors are characterized by a relatively small instruction set, where each instruction performs a single instruction, such as an arithmetic, logical, or load / store operation. Arithmetic and logic instructions take their operands from one or more general purpose registers (GPRs) and write their results to the GPRs. GPRs are structured registers. That is, a GPR includes discrete memory locations that are clearly identified in the instruction set structure and are directly addressable by instructions.

[0003] GPRs are often implemented in hardware such as an array of high-speed multi-port registers, each of which has a word width (eg, 32 or 64 bits) defined by the instruction set. This physical register array is called the physical register file (Ph...

Examples

Embodiment Construction

[0021] figure 2A functional block diagram of processor 10 is depicted. The processor 10 executes the instructions in the instruction execution pipeline 12 according to the control logic 14 . Pipeline 12 may be a superscalar design, with multiple parallel pipelines, such as 12a and 12b. Each pipeline 12a, 12b includes various registers or latches 16 organized into stages, and one or more arithmetic logic units (ALUs) 18 . Pipelines 12a, 12b fetch instructions from an instruction cache (I-cache or I$) 20 where memory addressing and permissions are managed by an instruction-side translation lookaside buffer (ITLB) 22 .

[0022] Data is accessed from a data cache (D-cache or D$) 24 where memory addressing and permissions are managed by a main translation lookaside buffer (TLB) 26 . In various embodiments, ITLB 22 may include a replica of a portion of TLB 26 . Alternatively, ITLB 22 and TLB 26 may be integrated. Similarly, in various embodiments of processor 10, I-cache 20 and...

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