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Handler and process for testing a semiconductor chips using the handler

A technology for loading chips and testing trays, which is applied in the field of manipulators and the process of testing semiconductor chips using the manipulators, and can solve problems such as difficult to effectively control unloading and loading processes, time constraints, etc.

Active Publication Date: 2011-11-23
MIRAE CORPORATION
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This not only makes it difficult to effectively control the unloading and loading process, but also places a limit on reducing the time required to unload the tested packaged chips from the test tray T and load the packaged chips to be electrically tested into the test tray T.

Method used

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  • Handler and process for testing a semiconductor chips using the handler
  • Handler and process for testing a semiconductor chips using the handler
  • Handler and process for testing a semiconductor chips using the handler

Examples

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Embodiment Construction

[0036] The preferred embodiments will now be discussed in detail, examples of which are illustrated in the accompanying drawings.

[0037] Such as Figure 3-9 As shown, a first embodiment of a manipulator 1 comprises a loading unit 2, an unloading unit 3, access locations 4, a chamber system 5 and a transfer unit.

[0038] The loading unit 2 performs a process of loading packaged chips to be electrically tested into a test tray. The loading unit 2 includes a loading stacker 21 , a loading picker 22 , a loading ascending / descending unit 23 , a loading guide member 24 , and a loading stopper 25 .

[0039] At the loading stacker 21, a plurality of customer trays each containing packaged chips to be electrically tested are stacked. The loading picker 22 picks up the packaged chips to be electrically tested from the uppermost customer tray at the loading stacker 21 . The loading unit 2 may include a plurality of loading stackers 21 .

[0040] The loading stacker 22 moves in the...

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PUM

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Abstract

A test handler includes a loading unit including a loading picker and a loading ascending / descending unit, an unloading unit including an unloading picker and an unloading ascending / descending unit, and a chamber system. A passage site connects the loading unit and the chamber system, and also connects the chamber system and the unloading unit. The arrangement of the handler reduces the time for the loading and unloading processes by performing the loading and unloading processes on separate test trays located at separate loading and unloading positions.

Description

technical field [0001] The present application discloses a test manipulator for transporting test trays containing packaged semiconductor chips so that electrical tests can be performed on the packaged chips, and also discloses a test manipulator for testing semiconductor chips using the manipulator craft. Background technique [0002] A test handler can be used to perform electrical tests on the packaged chips at the end of the packaging process. This manipulator transports packaged chips from user trays to test trays, and supplies the test trays loaded with packaged chips to a tester. The tester contains a test board with multiple sockets. The packaged chips in the test tray are brought into contact with the sockets to perform electrical tests on the packaged chips. Based on the test results, the packaged chips are graded, and then the manipulator transports the graded chips from the test tray to the appropriate customer tray according to the grade. [0003] figure 1 ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01R31/28G01R31/26
CPCG01R31/2867G01R31/26H01L22/00
Inventor 安正旭崔完凞朴海俊金炅泰
Owner MIRAE CORPORATION