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Mask for semiconductor device and patterning method using the same

A pattern and mask technology, applied in the field of masks of semiconductor devices, can solve problems such as difficulty in optimizing the optical proximity correction pattern 10

Inactive Publication Date: 2009-02-25
DONGBU HITEK CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, when the size of the pattern 10 is below 90 nm due to defects such as pinches and bridges, it is difficult to optimize the optical proximity correction pattern 10 to a desired size

Method used

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  • Mask for semiconductor device and patterning method using the same
  • Mask for semiconductor device and patterning method using the same
  • Mask for semiconductor device and patterning method using the same

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0021] Exemplary figure 2 is a plan view of a mask of a semiconductor device according to an embodiment of the present invention. see example figure 2 , the mask includes a first mask 110 and a second mask 120 , the first mask 110 includes a main pattern 112 , and the second mask 120 includes an auxiliary pattern 122 . The first mask 110 includes a light shielding region and a light transmissive region 118 on which a plurality of split patterns 114-1, 114-2, and 114 are formed. -3, the light-transmitting region 118 is other regions except the light-shielding region. More specifically, the light-shielding region includes a light-shielding layer formed on a substrate of the mask. The separated patterns 114-1, 114-2, and 114-3 serve to prevent light transmission. The light transmissive area 118 includes a mask substrate that allows light to transmit.

[0022] A plurality of separate patterns 114 - 1 , 114 - 2 and 114 - 3 together constitute the main pattern 112 . Each of ...

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Abstract

The invention discloses a mask for a semiconductor device and a patterning method using the same. The mask for a semiconductor device includes a first mask including main patterns constituted by a plurality of split patterns arranged at intervals, and a second mask including first auxiliary patterns disposed corresponding to regions among the plurality of split patterns, and second auxiliary patterns disposed corresponding to edge parts of the plurality of split patterns. The plurality of split patterns may be formed as triangles or squares. Because the main patterns of the first mask is arranged in space, the patterned marginal portion can be more accurate, and the pattern can be more close to match the original form; by independently controlling the main pattern and assistant pattern, the optical neighborhood correction can be optimized, and the optical resolution can be improved by using the first mask and second mask even if the pattern dimension is below 90nm.

Description

[0001] This application claims priority under US Code 119-35 of Korean Patent Application No. 10-2007-0084931 (filed August 23, 2007), the entire contents of which are incorporated herein by reference. technical field [0002] The present invention relates to a mask for a semiconductor device and a patterning method using the mask, and more particularly to a mask for a semiconductor device capable of improving accuracy of line resolution and a pattern using the mask method. Background technique [0003] Mask patterning techniques can have a serious impact on the accuracy of patterns formed on semiconductor substrates. In order to improve the accuracy of patterns, masks used for semiconductor devices should be precisely designed so that the brightness of light passing through the masks can be properly adjusted. For this purpose, there is an increasing need to develop new photosensitizers, scanners equipped with high numerical aperture lenses, and improved masking techniques ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G03F1/14G03F7/20H01L21/027
CPCG03F1/144G03F1/36G03F1/70G03F1/38G03F1/66H01L21/0274H01L21/0337
Inventor 李峻硕
Owner DONGBU HITEK CO LTD
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