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Transitioning a processor package to a low power state

A low-power state, processor technology, used in data processing power supplies, electrical digital data processing, digital data processing components, etc., can solve the problems of long entry/exit response time, unavailability, performance loss, etc.

Inactive Publication Date: 2009-06-17
INTEL CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Because encapsulating non-zero C-state entry / exit latency is relatively long (e.g., around 100 to 200 microseconds (μs)), it is usually not worth using this state for the short time that all cores are idle, or a performance penalty will occur
So the OS cannot take advantage of the lower power states of the package, causing the package to always run in a higher power state than needed

Method used

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  • Transitioning a processor package to a low power state
  • Transitioning a processor package to a low power state
  • Transitioning a processor package to a low power state

Examples

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Embodiment Construction

[0015] Embodiments may reschedule / delay tasks so that the idle time of all cores of the package can be aligned and extended. This way, there are more opportunities to use larger low power states, ie deeper non-zero packed C-states. Embodiments may operate at a relatively fine-grained granularity, such as every 500 microseconds (μs), so that latency-sensitive workloads do not degrade performance. In contrast, the conventional OS scheduler just makes all tasks time as they are set.

[0016] In various embodiments, a predetermined interval may be set, eg, 500 microseconds, and within each interval break event processing may be delayed to keep cores in the same package idle and busy together. Furthermore, busy times can be stitched to be continuous (ie not separated by short idles) so that idle durations can be extended to accommodate long entry / exit latency of package depth non-zero C-states. As described below, a prediction of future core usage, ie, the next operating interval...

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Abstract

In one embodiment, a processor package is controlled to be in a package low power state for a first portion of an operation interval and in a package active state for a second portion of the operation interval. To enable the low power state, operations scheduled during the first portion are delayed until the second portion. Other embodiments are described and claimed.

Description

technical field [0001] The present invention relates to transitioning a processor package into a low power state. Background technique [0002] Power and thermal management in all parts of computer-based systems has become more challenging than ever. While in the server world, electricity costs drive the need for low-power systems, battery life and thermal limits also make these issues significant in mobile systems. An operating system (OS) is often used to control hardware components to optimize the system for maximum performance with minimum power consumption. Most modern OSes use Advanced Configuration and Power Interface (ACPI) standards, such as Rev. 3.0b published October 10, 2006, to optimize systems in these areas. Implementations of ACPI allow the core to be in different power-saving states (also known as low-power or idle states), these states are often referred to as the so-called C1 to Cn states. Similar package C-states exist for package-level power savings. ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F1/32
CPCY02B60/144G06F1/3203G06F1/329Y02B60/32Y02D10/00Y02D30/50
Inventor J·宋Q·刁
Owner INTEL CORP