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Etching method and dual damascene structure forming method

A technology of etching gas and etching time, used in electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve problems such as uniformity and poor consistency, achieve uniform polymer distribution, improve uniformity, and improve etching quality effect

Active Publication Date: 2011-01-12
SEMICON MFG INT (SHANGHAI) CORP
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  • Abstract
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  • Claims
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Problems solved by technology

[0015] In addition, for through holes with different aperture sizes, similar problems will occur due to the etching size effect
This will lead to poor uniformity and consistency between devices formed on the same substrate

Method used

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  • Etching method and dual damascene structure forming method
  • Etching method and dual damascene structure forming method
  • Etching method and dual damascene structure forming method

Examples

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no. 1 example

[0085] In this embodiment, through holes (or contact holes) are formed in the dielectric layer by using the etching method of the present invention.

[0086] Figure 7 It is a flow chart of the etching method in the first embodiment of the present invention, Figure 8 to Figure 12 In order to illustrate the device cross-sectional view of the etching method of the first embodiment of the present invention, below in conjunction with Figure 7 to Figure 12 The first embodiment of the present invention will be described in detail.

[0087] Step 701: Provide a substrate with a dielectric layer on the substrate.

[0088] The substrate in this embodiment may be a substrate on which metal-oxide-semiconductor transistors have been formed, or a substrate on which an underlying metal wiring structure has been formed (not shown in the figure).

[0089] In addition, in order to improve the uniformity and consistency of the etching pattern in terms of etching depth, usually an etching st...

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Abstract

The invention discloses an etching method, which includes steps of providing a substrate equipped with a dielectric layer, defining etching patterns on the dielectric layer, utilizing a first etching gas to carry out first etching to the dielectric layer, and utilizing a second etching gas to carry out second etching to the dielectric layer, wherein polymer generated by the second etching gas is less than that generated by the first etching gas. The invention further discloses a corresponding method of forming a corresponding dual damascene structure, and poor uniformity in the existing etching method can be improved by adopting the etching method and the method of forming a corresponding dual damascene structure, thereby increasing the formed quality of etched patterns and the dual damascene structure.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to an etching method and a method for forming a double damascene structure. Background technique [0002] With the integration of chips getting higher and higher, the size of components is getting smaller and smaller, and various effects caused by the high density and small size of devices have an increasingly prominent impact on the results of semiconductor process manufacturing. [0003] Taking the etching process as an example, due to different specific functions, the size, shape and distribution density of each etching pattern on the same substrate may be different. When the device size is small to a certain extent, even if it is formed after the same etching process Results of etched patterns on the same substrate may also vary: [0004] For small-sized etched pattern parts, the etching rate will be relatively low due to the size-dependent etching effect (S...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/311H01L21/768
Inventor 孙武王新鹏
Owner SEMICON MFG INT (SHANGHAI) CORP
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