Semiconductor device including a dopant blocking superlattice and associated methods

Abstract

A semiconductor device may include at least one metal oxide field-effect transistor (MOSFET). The at least one MOSFET may include a body, a channel layer adjacent the body, and a dopant blocking superlattice between the body and the channel layer. The dopant blocking superlattice may include a plurality of stacked groups of layers. Each group of layers of the dopant blocking superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Description

Technical field [0001] The present invention relates to the field of semiconductors, and more specifically, to semiconductors with enhanced performance such as energy band engineering-based semiconductors and related methods. Background technique [0002] Various structures and techniques have been proposed to enhance the performance of semiconductor devices, such as by increasing the mobility of charge carriers. For example, US Patent Application 2003 / 0057416 by Currie et al. discloses strained material layers of silicon, silicon-germanium, and relaxed silicon, and also includes impurity-free regions that may additionally cause performance degradation. The resulting biaxial strain in the upper silicon layer changes the carrier mobility, enabling higher speed and / or lower power devices. Published US Patent Application 2003 / 0034529 by Fitzgerald et al. discloses CMOS inverters that are also based on similar strained silicon technology. [0003] Takagi's US Patent No. 6,472,685 B2 ...

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