Efficient interrupt return address save mechanism

Abstract

A system, apparatus and method for efficiently processing interrupts using general purpose registers in a pipelined processor. In accordance with the present disclosure, a register file may be updated to efficiently save an interrupt return address. When an interrupt request is received by the system's processor, or when the request is issued in the execution of a program, a pseudo-instruction is generated. This pseudo-instruction travels down the pipeline in the same way as other instructions and updates the register file by causing the register file to be written with the return address of the last instruction for which processing has not been completed.

Description

technical field [0001] The present invention relates generally to processors, and more particularly to pipelined processors that update register files to efficiently save interrupt return addresses. Background technique [0002] Achieving higher computer processing speeds has always been a goal of manufacturers as well as a goal of users. For the purpose of enhancing high-speed processing, some computer processors employ a technique called pipeline processing. Processors incorporating a pipelined architecture allow multiple instructions to exist simultaneously in various execution stages. [0003] In a pipelined architecture, a single instruction loop can contain five stages. These stages can be described in order as follows: (1) fetch; (2) decode; (3) access register file; (4) execute; and (5) write to register file. In pipeline processing, processing in each of these stages is performed in parallel to achieve high-speed processing. Pipelining can be used to increase pr...

AI Technical Summary

Problems solved by technology

All of these complexities make it difficult to simply provide additional ports to the register file to hold interrupt return addresses or provide special control paths to share existing register file ports to hold interrupt return addresses

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