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Low power consumption multi-mode programmable frequency divider

A low-power, frequency divider technology, used in pulse counters, counting chain pulse counters, electrical components, etc., can solve problems such as wasted power consumption, and achieve the effect of reducing power consumption, simple circuit structure, and power saving

Inactive Publication Date: 2010-10-27
SOUTHEAST UNIV
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Problems solved by technology

[0006] Technical problem: The purpose of this invention is to provide a low-power multi-mode programmable frequency divider, which solves the problem that a considerable part of the existing cascaded multi-mode programmable frequency divider is wasted under certain frequency division ratios. The problem of power consumption

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  • Low power consumption multi-mode programmable frequency divider
  • Low power consumption multi-mode programmable frequency divider

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Embodiment Construction

[0023] At present, the high-speed and wide-range programmable frequency divider with integer step size is realized by cascading the traditional 2 / 3 frequency division units, such as figure 1 shown. The mode control output signal Mo only needs to be fed forward step by step, so it has a strong speed advantage and has a very convenient binary control bit. In order to take advantage of these advantages of this structure and realize the characteristics of low power consumption, we adopt a method of timely turning off the tail current of the latch that does not participate in the overall work.

[0024] figure 2 It is a structural diagram of a traditional 2 / 3 frequency division unit. It contains four latches and three AND gates, the first latch 21 and the second latch 22 form a basic division by 2 mode, and the third latch 23 and the fourth latch 24 Swallow pulse signals are provided for the first two stages of latches, so that the entire frequency division unit can work in the ...

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Abstract

A low power consumption multi-mode programmable frequency divider comprises a 2 / 3 frequency dividing unit and an OR-gate network which are in grade connection. The output of each grade of the OR-gate network and the frequency dividing ratio setting end of the 23 unit jointly control the cut-off of the tail current supply of the corresponding flip-latch inside each 2 / 3 unit for saving power consumption. The flip-latch unit inside each 2 / 3 unit adopts the traditional supply coupling structure and an improved supply coupling structure with a switch control based on the same. As the circuit structure of the invention is simple, during even number frequency division over 25% of power consumption can be saved, and at utmost 50% of power consumption can be saved. Under different frequency dividing ration, about 21% of power consumption can be saved in average.

Description

technical field [0001] The invention relates to the design of a frequency divider, in particular to the technical field of low power consumption multi-mode programmable frequency divider design. Background technique [0002] Due to the rapid development of large-scale integrated circuits, wireless communication technology has been widely used, so high-performance wireless transceivers have become a research hotspot in recent years. Among them, the frequency synthesizer plays a vital role in ensuring the performance of the transceiver, and the frequency divider is one of the important modules in the frequency synthesizer. [0003] At present, with the gradual reduction of IC process size and the popularization of personal terminals, low power consumption and fully integrated products have become the mainstream of design. Lower power consumption can extend the life of the battery and maintain a longer standby time. Therefore, products with low power consumption are of great ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K23/66
Inventor 吴建辉王声扬张萌李红刘万福李东明吉新村
Owner SOUTHEAST UNIV
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