Multi-modulus frequency divider with extended and continuous dividable frequency range

Abstract

The invention relates to a multi-modulus frequency divider with an extended and continuous dividable frequency range, which comprises a multi-modulus frequency dividing circuit, a pulse generating circuit and a modulus signal generating circuit, wherein the multi-modulus frequency dividing circuit generates an output frequency according to an input frequency and a divisor, and a numerical range of the divisor can be divided into a plurality of numerical intervals; the pulse generating circuit is used for generating a pulse signal; the modulus signal generating circuit judges that the divisor belongs to which numerical interval and generates a judging result, and inputs the pulse signal generated by the pulse generating circuit into a specific frequency dividing unit in the multi-modulus frequency dividing circuit according to the judging result; and the pulse signal is used as one of references for the specific frequency dividing unit when outputting a modulus signal, so that the multi-modulus dividable frequency divider can correctly read the divisor.

Description

technical field [0001] The invention relates to a multi-modulus divider, in particular to a multi-modulus divider with an extended and continuous divisible frequency range. Background technique [0002] In order to achieve increasingly complex communication specifications, frequency synthesizers used in communication systems are required to have a wide range of frequency synthesis capabilities to match various crystal oscillators of different specifications, and in addition to integer multiples In addition, the ability to synthesize non-integer multiples of frequencies is also possible. figure 1 It is a structural schematic diagram showing a programmable (programmable) frequency division circuit 100 commonly used in frequency synthesizers, which includes N serially connected frequency division units (divider cells) 110 (N=6 in this example), and each A divider unit 110 is subject to a programming input signal P IN control to perform frequency division by 2 or 3 (wherein, P...

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Problems solved by technology

For example, if K=6, please refer to image 3 , which is the modulus signal MO of the frequency division circuit 200 when the divisor jumps from 63 to 64 1 -MO 6 It can be seen from the figure that the frequency division unit 110f is bypassed in the divisor cycle when the divisor is less than 64 (that is, the divisor cycle of 62 and 63 in the figure), so that the modulus signal MO 6 Only with FO 6 related, so the modulus signal MO 6 The cycle is 2-3 times longer than the desired cycle (at this time, MO 1 -MO 5 The period of the input P IN The corresponding cycle value is the required cycle value), causing the modulus signal MO to enter the divisor cycle when the divisor is equal to 64 6 is still maintained in the logic '0' state, the frequency division unit 110f cannot read P IN_5 , and in order not to make the divisor become 0, at this time the frequency division circuit 200 forces P IN_4 The carry is 1, and the divisor cycle that should have been divided by 64 becomes divided by 32, causing the multi-modulus frequency divider to output an incorrect frequency

For the entire frequency synthesizer, this error will be reflected to the output through the mechanism of narrow frequency modulation (Narrow band FM), causing the entire phase noise to become very bad and unbearable, and even cause lock-out.

[0005] In short, although the frequency divider circuit 200 is nominally divisible by a value range of 2 M -2 (N+1) -1, but only if the divisor range does not exceed 2 M -2 (M+1) -1, 2 M+1 -2 (M+2) -1..., and 2 N -2 (N+1) -1 and other intervals, it can be guaranteed that the output frequency of the multi-modulus frequency divider will not produce errors, but in the entire value interval 2 M -2 (N+1) -1 does not guarantee that each frequency division can be correctly divided within a frequency division cycle

[0006] However, in today's application trend, the same circuit must be able to support different reference frequencies (the reference frequency changes with crystal oscillators of different specifications, such as: GSM=13MHz or 26MHz, CDMA=19.2-19.8MHz, GPS= 16MHz, WCDMA=15.36MHz...), for example, a GPS chip uses a 16MHz crystal oscillator when it is used alone, but when it is used with a mobile phone application, it must be able to support the reference frequency of the mobile phone 13MHz or 26MHz, and when the crystal specification supported Many times, non-integer-N frequency synthesizers are hard to avoid encountering division values ​​from less than 2 K value jumps to greater than or equal to 2 K The change of the value, at this time the aforementioned frequency division circuit 200 is not applicable

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