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Semiconductor device manufacturing method

一种制造方法、半导体的技术,应用在半导体/固态器件制造、半导体器件、半导体/固态器件零部件等方向,能够解决焊剂成分、柱电极高度偏差、柱电极的下部与电极不能接合等问题

Inactive Publication Date: 2009-09-30
FUJI ELECTRIC CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In addition, since the solder material is pasty, there is a problem that flux components or solder material scatter during reflow.
[0011] In addition, with the recent miniaturization of semiconductor elements, the weight of the semiconductor element 105 itself has become lighter. If a paste-like solder material is applied by printing, the semiconductor element 105 will move, and the application position of the paste-like solder will occur. problems such as deviation
[0012] Furthermore, there are variations in the heights of the post electrodes 112a, and in post electrodes with a relatively short distance, there is a problem that the lower part of the post electrodes and the electrodes cannot be sufficiently bonded through the solder layer.

Method used

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Experimental program
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no. 1 approach

[0059] Hereinafter, the method of manufacturing the semiconductor device according to the first embodiment will be described in detail with reference to the drawings.

[0060] figure 1 It is a flowchart for explaining the manufacturing method of the semiconductor device of 1st Embodiment. In the manufacturing method of the semiconductor device according to the first embodiment, for example, a case where a vertical IGBT (Insulated Gate Bipolar Transistor: Insulated Gate Bipolar Transistor) element is used as a semiconductor element is exemplified. The semiconductor element used in the manufacturing method is not limited to the IGBT element.

[0061] First, prepare a semiconductor element (step S1), the semiconductor element is respectively provided with at least one gate electrode (first electrode) as a control electrode and an emitter electrode (second electrode) as a main electrode, and has a gate electrode (second electrode) configured to be connected to the gate electrode...

no. 2 approach

[0202] Next, use Figure 14 ~ Figure 19 A specific manufacturing method of the semiconductor device manufacturing method of the second embodiment will be described. In addition, in all the drawings shown below, the above-mentioned Figure 2 to Figure 13 The same symbols are assigned to the same components, and detailed description thereof will be omitted.

[0203] Figure 14 ~ Figure 19 It is a figure for demonstrating the manufacturing method of the semiconductor device of 2nd Embodiment.

[0204] First, if Figure 14 As shown, semiconductor elements 10, 15 are prepared. These semiconductor elements 10 and 15 are fixed and supported by carbon fixing jigs (not shown).

[0205]Next, the sheet-shaped solder material (first conductive bonding material) 11 is supported by the insulating layer 10i disposed on the upper surface side of the semiconductor element 10, so that the main surface of the solder material 11 faces the gate electrode 10g and the emitter electrodes 10ea, 1...

no. 3 approach

[0264] Next, use Figure 20 A specific manufacturing method of the semiconductor device manufacturing method of the third embodiment will be described. In addition, in all the drawings shown below, the above-mentioned Figure 2 to Figure 19 The same symbols are assigned to the same components, and detailed description thereof will be omitted.

[0265] Figure 20 Modifications of the semiconductor element 10 used in the method of manufacturing the semiconductor device according to the third embodiment are exemplified in FIG. here, Figure 20 (a), Figure 20 (b), Figure 20 (c), means along the figure 2 A cross-sectional view of the semiconductor element 10 at the position of the dotted line X—Y.

[0266] For example, the insulating layer 10i that separates the gate electrode 10g and the emitter electrode 10ea of ​​the semiconductor element 10, or the insulating layer 10i between the emitter electrodes 10ea and 10eb, such as Figure 20 As shown in (a), it may be tapered...

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PUM

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Abstract

The invention provides a semiconductor device manufacturing method, which is object to improve the reliability and manufacture yield of the semiconductor apparatus. A semiconductor element has a first electrode and a second electrode separated by an insulation layer, a bonding material is configured on the metal foil, and the semiconductor element is placed on the bonding material in a mode of contacting it with a third electrode. In addition, the sheet-shape second conductive bonding material is opposite to the first electrode and the second electrode of the semiconductor element, and the lower end of the post electrode is opposite to the upper surfaces of the first electrode and the second electrode with bonding material intervening therebetween. And the welding material is separated byan insulation layer, the first electrode is connected to the post electrode through bonding material. Furthermore, the third electrode is jointed to the metal foil through bonding material. Therefore, the reliability and manufacture yield of the semiconductor apparatus can be improved.

Description

technical field [0001] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device on which a plurality of power semiconductor elements are mounted. Background technique [0002] In an inverter device, an uninterruptible power supply device, a machine tool, an industrial robot, etc., a semiconductor device mounted with a plurality of power semiconductor elements is used independently of its main device. Furthermore, recently, a semiconductor device of a wireless structure that does not use bonding wires has attracted attention in order to pass more large currents (for example, refer to Patent Document 1). [0003] Figure 21 It is a figure of main part of the semiconductor device of a wireless structure. [0004] The illustrated semiconductor device 100 has a metal base plate 101, an insulating plate 102 bonded to the metal base plate 101, and conductive patterns 103a, 103b, 103...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/50H01L21/60
CPCH01L2924/01032H01L2224/29109H01L2924/0105H01L2224/27013H01L24/32H01L2924/13091H01L2224/83365H01L2924/0132H01L2924/19041H01L2924/01013H01L2224/32225H01L2924/0665H01L25/50H01L2224/2919H01L2924/157H01L2924/19043H01L2924/0133H01L2224/838H01L24/83H05K2201/10969H01L2924/01033H01L2924/01074H01L2924/01078H05K2201/1059H01L2924/01051H01L2924/13055H01L2924/01015H01L2924/01023H01L2924/01082H01L23/5385H05K1/145H01L24/73H01L2224/83101H01L2924/30105H05K3/34H01L2924/01322H01L2924/01029H01L2224/29111H01L2924/014H05K2201/10962H01L2924/0135H01L2224/291H01L24/33H01L24/01H01L2924/01047H01L2924/01079H01L2924/01005H01L2924/01006H01L25/072H01L2924/0102H05K2201/10303H01L24/91H01L2224/83051H05K2203/0405H05K2201/10166H01L2224/26145H01L2924/1305H01L2924/1306H01L2924/00H01L2924/07025H01L2924/01083H01L2924/01049H01L2924/01028
Inventor 谷口春隆池田良成
Owner FUJI ELECTRIC CO LTD
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