Multichip package structure capable of arranging chips on pins

Abstract

The invention discloses a multichip package structure capable of arranging chips on pins. The multichip package structure mainly comprises two or more two pins, a first chip arranged on the pins, a second chip or more second chips overlaid on the first chip and an adhesive body; the inner parts of the pins, which are in the adhesive body, are completely sunken on the same plane so that the inner parts of the pins are completely parallel to the upper surface and the lower surface of the adhesive body; the height distance between the inner parts of the pins and the upper surface of the adhesive body is three times or more of the height distance between the inner parts of the pins and the lower surface of the adhesive body; and the quantity of the second chip(s) is proper so that the thickness between the upper surface of the adhesive body and the nearest second chip is approximately identical to the height distance between the inner parts of the pins and the lower surface of the adhesive body. The balance of upper mold flow and lower mold flow can be achieved although the inner parts of the pins are not bent for sinking, therefore the pins supporting the multiple chips cannot displace or incline.

Description

technical field [0001] The present invention relates to a semiconductor device, in particular to a chip-on-lead (COL, Chip-On-Lead) multi-chip packaging structure. Background technique [0002] In the traditional semiconductor packaging structure, the lead frame can be used as a chip carrier and an electrical transfer medium. Depending on the way the chip is carried, the packaging form can be divided into: chip on the lead (COL, Chip-On-Lead), lead The pin is on the chip (LOC, Lead-On-Chip) and the chip is carried on the chip pad (die pad) of the lead frame. Wherein, "the chip is on the lead" refers to adhering the back of the chip (ie, the surface without integrated circuits) to the inner section of the lead, and then sealing the chip and the lead with an encapsulant. In order to achieve a balance between the upper and lower mold flow during the injection molding process, the tie bar of the lead or chip pad is usually made into multiple sinking bends, which will cause the ...

AI Technical Summary

Problems solved by technology

In addition, in order to prevent the second chip 140 from mistakenly touching the first bonding wires 160 located below, a spacer 190 is usually provided between the first chip 130 and the second chip 140, but this also shortens the possible time of the chip. stack height without being able to stack more chips

Because the peripheral portion of the second chip 140 that is not bonded to the spacer 190 (including the portion where these second solder pads 143 are formed) cannot obtain support from the spacer 190 and become a floating position when bonding, in order To make these second bonding wires 170 have better wire bonding support, the second chip 140 must have a certain thickness, but this also limits the number of chips that can be stacked.

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