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Method for correcting lug photomask pattern

A photomask and pattern technology, applied in the field of bump formation, can solve problems such as inability to design invalid chips, high defect rate, and shading

Active Publication Date: 2010-01-06
CHIPMOS TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, the performance of the alignment exposure machine such as photoresist profile, alignment error and high defect rate are its disadvantages
However, the stepper aligner cannot be designed to cover all invalid chips when making a photomask, so in the subsequent process of electroplating gold bumps, some gold bumps will be formed on the On the invalid chip, the gold bumps formed on the invalid chip will be removed during the process, resulting in a waste of process cost

Method used

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  • Method for correcting lug photomask pattern
  • Method for correcting lug photomask pattern
  • Method for correcting lug photomask pattern

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Embodiment Construction

[0015] The direction that the present invention discusses here is a method for modifying the photomask pattern of bumps, which is to use two photomasks and cooperate with positive photoresists so that bumps are only formed on the effective area of ​​the wafer. . In order to provide a thorough understanding of the present invention, detailed steps and components thereof will be set forth in the following description. Here, the well-known method of forming bumps on the chip and the detailed steps of the back-end process such as chip thinning are not described in detail to avoid unnecessary limitations of the present invention. However, for the preferred embodiments of the present invention, it will be described in detail as follows, but in addition to these detailed descriptions, the present invention can also be widely implemented in other embodiments, and the scope of the present invention is not limited. Subsequent patent scope shall prevail.

[0016] refer to figure 1 , i...

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Abstract

The invention relates to a method for correcting a lug photomask pattern, including that: a wafer which is provided with a plurality of bonding pads on an active surface is provided; photoresist layer is formed on the active surface of the wafer; a first photomask layer with a first pattern is provided, wherein the first pattern of the first photomask layer is used for limiting the effective area on the wafer, and the effective area is corresponding to the whole area of the wafer; a primary exposure process is executed, so that the first pattern is transferred onto the photoresist layer; the first photomask layer with the first pattern is substituted by a second photomask layer with a second pattern, and a secondary exposure process is executed, so that the second pattern is transferred onto the photoresist layer, wherein the second pattern of the second photomask layer is used for limiting partial area of the wafer, and partial second pattern is overlapped with partial first pattern; and a developing and etching process is executed to remove the overlapped part of the second pattern and the first pattern, and a plurality of bonding pads on the effective area on the wafer are exposed and partial photoresist layer on the ineffective area on the whole area is removed.

Description

technical field [0001] The present invention relates to a method of forming bumps, and more particularly to a method of utilizing two photomask steps to avoid forming bumps on invalid chip areas of a wafer. Background technique [0002] In the semiconductor lithography process, a mask aligner can perform alignment and exposure of the entire wafer. Because it is a full-frame, it only needs to cover all invalid chips when making a photomask. However, the performance of the alignment exposure machine such as photoresist profile, alignment error and high defect rate are its disadvantages. However, the stepper aligner cannot be designed to cover all invalid chips when making a photomask, so in the subsequent process of electroplating gold bumps, some gold bumps will be formed on the On the invalid chip, the gold bumps formed on the invalid chip will be removed during the process, resulting in a waste of process cost. Contents of the invention [0003] In view of the above pr...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G03F1/14G03F7/00G03F7/039G03F7/20H01L21/00G03F1/76
Inventor 傅文勇
Owner CHIPMOS TECH INC