Safety JTAG module and method for protecting safety of information inside chip

Abstract

The invention relates to a safety JTAG circuit and a method for protecting the security of information inside a chip. The safety JTAG circuit connected between a JTAG port and a protected object comprises a nonvolatile medium, a loading circuit, a security attribute control register, a TAP controller, a first selector, a second selector, a switch, a password authentication circuit and a logic processing circuit. The TAP controller and the two selectors are connected between the JTAG port and the protected object. The switch is switched by the control of a timer. The password authentication circuit is used for authenticating whether a clear-text password input by a user is accordant with a fuzzification password or not. The logic processing circuit is used for logically processing an authentication result output by the password authentication circuit and an indication signal output by the security attribute control register and outputting an enable signal to the two selectors so as to control whether the JTAG port is allowed to be connected with the protected object inside the chip through the TAP controller or not. The invention ensures the security and the convenience of an SOC chip in testing and debugging processes, thereby protecting the security of data inside the chip.

Description

technical field [0001] The present invention relates to the security control technology of SOC chip JTAG port, especially relate to a kind of security JTAG circuit that carries out security control to processor JTAG circuit, memory test circuit and full scan chain test circuit inside SOC chip, and application of the security JTAG Circuits to realize the method of protecting the information security inside the chip. Background technique [0002] Testing and debugging is an important link in the design and production of SOC (System-on-Chip) chips. The test is used to ensure that the SOC chip can work normally, and the purpose of debugging is mainly to facilitate the application development or fault tracking analysis of the chip. [0003] For the debugging of the integrated processor (central processing unit, microprocessor) of the SOC chip, the JTAG (Join Test Action Group) port is mainly used. The user can control the processor to execute the instruction expected by the use...

AI Technical Summary

Problems solved by technology

The existing technology has considered the potential safety hazards of SOC chip debugging, but the overall safety of the test is insufficient.

[0005] For example, the Chinese patent applications with application numbers 200410003197 and 200610050898 respectively provide a technical solution to solve the above-mentioned potential safety hazard caused by the JTAG port from the perspective of chip debugging, but there are the following defects: the technical solutions provided by these two patent applications It is suitable for one-time mass programming, and it is not convenient for personalized distribution and multi-party development; the personalized distribution here means that in the case of JTAG protection, user A can only access the content that user A can access through the JTAG port, but cannot access The content that user B can access; In addition, these two patent applications only provide two options: off or on, and do not use the tracking and analysis of chip failures after productization

The user may even open the closed JTAG port through the full scan chain test technology, thereby invalidating the JTAG port protection measures

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