Programmable self-test for random access memories

Abstract

A system that provides large instruction sets for testing memory yet reduces area overhead is disclosed. The system for testing a memory of an integrated circuit comprises a set of registers providing element based programmability for a plurality of tests, wherein each test includes a plurality of test elements; a finite state machine for receiving a plurality of test instructions from the set of registers, wherein the finite state machine dispatches signals instructing a test pattern generator to generate a test pattern; a memory control module for applying the generated test pattern to the memory; and a comparator module for comparing a response received from the memory to a stored, known response.

Description

technical field [0001] The content disclosed in the present invention generally relates to the field of integrated circuits, and more specifically, relates to a programmable built-in self-testing structure and a corresponding testing method for testing one memory or multiple memories of an integrated circuit. Background technique [0002] Integrated circuit (IC) technology has been continuously improved, including scaling down device geometries to achieve lower manufacturing costs, higher device integration density, higher speed and better performance. These improvements provide the best quality for the IC. Typically, ICs are inspected after fabrication to ensure that the ICs exhibit the desired quality. Inspection typically involves applying a stimulus to the IC under inspection, obtaining and analyzing the response of the IC device, and comparing the response of the device to a known, desired response. In the testing of the IC's memory, one approach involves programmable...

AI Technical Summary

Problems solved by technology

However, when testing complex memory devices, slave embedded memory requires a large instruction set, which results in a larger area overhead than desired

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