Abnormality monitoring method and device

Abstract

The invention discloses an abnormality monitoring method and a device, and the adoption of the technical scheme of the embodiment of the invention is as follows: the method monitors whether the state of a PCI Express device is abnormal or not, when a central processing unit sends a read request data packet to the PCI Express device and the state of the PCI Express device is abnormal, at least packet header information of the current read request data packet is obtained, a read completion data packet is generated according to the packet header information, the read completion data packet indicates the abnormality of the completion state and the read completion data packet is sent to the central processing unit for leading the central processing unit to do the abnormality treatment. The method and the device can solve the technical problem that in the prior art, when the central processing unit is reading data of the PCI Express device, if the PCI Express device is abnormal, then the central processing unit can not receive the read completion data packet from the PCI Express device, thereby causing hanging-up of the treatment task of the central processing unit.

Description

technical field [0001] The invention relates to abnormality monitoring technology, in particular to an abnormality monitoring method and device. Background technique [0002] The PCI Express (Peripheral Component Interconnect Express, high-performance peripheral device interconnection bus) protocol stipulates that the initiator of a PCI Express transaction is a requester, and the receiver of a PCI Express transaction is a completer. When the requester initiates a read request packet, the completer needs to return a read completion packet within a specified time as a response to the read request packet. The PCI Express protocol also clearly defines that the requester must implement a completion timeout mechanism, the purpose of which is to detect when an appropriate read completion packet has not been returned. The PCI Express protocol also defines the allowable range of timeout, and the device must generate a timeout within 50ms. [0003] For example: when supposing that r...

AI Technical Summary

Problems solved by technology

[0005] When the CPU is reading the data of the PCI Express device, if the PCI Express device is abnormal, the CPU will not be able to receive the read completion packet from the PCI Express device, which will cause the processing task of the CPU to hang

For example: incorrect hot unplugging of PCI Express devices or link reset operations of PCI Express devices will make the CPU unable to receive read completion packets from PCI Express devices, causing CPU processing tasks to hang

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