Method and system for controlling reading transfer among buses with different speeds

Abstract

The invention discloses a method for controlling reading transfer among buses with different speeds, which includes following steps that a lateral interface of a bridge equipment B-class bus sends a B-class bus reading request of data on one side of an A-class bus requested by equipment on a B-class bus, sends an address of the reading request of the B-class bus and data identification to request FIFO, reads request data from reading FIFO and returns the data to the equipment on the B-class bus; and a lateral interface of a bridge equipment A-class bus takes out the reading request of the B-class bus after seeing the reading request of the B-class bus from the request FIFO, begins to send reading request of an A-class bus on the A-class bus, performs data prefetch of two stages for reading data request by reading request of the B-class bus, and sends the reading data returned from the A-class bus to the reading FIFO.

Description

technical field [0001] The invention relates to the technical field of computer system data transmission, in particular to a control method and system for reading transmission between buses with different speeds. Background technique [0002] In computer systems, a chip called a bridge is usually used to isolate different buses from each other. When a device on one bus wants to request resources on another bus, the bridge is responsible for converting the operation on this bus into the operation on the bus where the requested resource resides. Due to the physical and structural limitations of the bus, only a limited number of devices can be mounted on each bus. Therefore, many computer systems use multiple isolated buses in structure to provide expansion of system functions. These mutually isolated buses can use the same protocol or different protocols. The protocol conversion between different buses is done by the bridge used to isolate these buses. After the conversion...

AI Technical Summary

Problems solved by technology

The deficiency of this method is: read FIFO and write FIFO need more complicated control logic to indicate the length of valid data in FIFO, write data and need to stay longer time in write FIFO, in order to improve the bus of initiator bus when data transmission Efficiency requires larger depth write FIFO and read FIFO

Both of the above two patents have the same defect: that is, there is a problem of excessive prefetching of data when a read transfer is initiated between buses of different speeds

In addition, the method disclosed in the Chinese patent No. ZL200510086446.1 also exists: the length of the longest single data transfer that can occur on the bus is limited by the depth of the read FIFO when a read request transfer is initiated between buses of different speeds defect

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