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Cascading add-compare-select unit in convolutional code Viterbi decoder and data processing method thereof

A data processing, addition and selection technology, applied in the field of communication channel coding and decoding, to achieve the effect of increased decoding speed and high-speed decoding speed

Inactive Publication Date: 2010-06-16
BEIHANG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] In order to solve the deficiencies in the prior art, the present invention provides a design method of the addition ratio selection unit ACSU in a convolutional code Viterbi decoder to solve the problem of high-speed decoding with low hardware resource consumption

Method used

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  • Cascading add-compare-select unit in convolutional code Viterbi decoder and data processing method thereof
  • Cascading add-compare-select unit in convolutional code Viterbi decoder and data processing method thereof
  • Cascading add-compare-select unit in convolutional code Viterbi decoder and data processing method thereof

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Embodiment 1

[0042] Example 1: (2,1,7) An embodiment of the 2-stage addition and comparison selection unit ACSU of the convolutional code.

[0043] The convolutional codes used in the embodiments are first described, as figure 1 Shown coder structure, what used in the present embodiment is (2,1,7) convolutional code that meets CCSDS standard, generator polynomial is (171,133), and this convolutional code is that every 2bits when decoding is 1 set of input decoders.

[0044] The data input by the decoder calculates the branch metric value in the branch metric unit BMU, such as figure 2 , the input of each stage of the cascaded ACSU is the branch metric value bm and the state value pm of each state, and the output is the new state value and surviving path value of each state.

[0045] When performing addition, comparison and selection calculations, the branch metric values ​​corresponding to each state are added to the state value, and the minimum value corresponding to each state is se...

Embodiment 2

[0057] Example 2: (2,1,7) 3 stages of convolutional codes add the embodiment of ratio selection unit ACSU;

[0058] Such as Figure 7 As shown, the 3-stage addition and comparison selection unit ACSU in the present invention requires the decoding input of the previous stage to be 6 bits, and the branch measurement value given by the branch measurement unit BMU has 12 data, which are divided into three groups. In this embodiment, the 3-stage plus comparison selection unit ACSU is obtained by cascading the 3-stage 64-state plus comparison selection unit GACSU.

[0059] The calculation process of the 3-level addition and comparison selection unit ACSU is basically the same as that of the 2-level addition and comparison selection unit ACSU, except that in the first step, three groups of branch metric values ​​are required, and in the second step, three levels of 64 Calculation of state plus ratio selection unit GACSU.

[0060] The calculation process of the add ratio selection...

Embodiment 3

[0069] Example 3: The embodiment of 4 grades of addition ratio selection unit ACSU:

[0070] Such as Figure 8 , the 4-stage addition and comparison selection unit ACSU in this embodiment requires the decoding input of the previous stage to be 8 bits, and the branch measurement value given by the branch measurement unit has 16 data, which are divided into four groups. In this embodiment, the 4-stage plus comparison selection unit ACSU is obtained by cascading the 4-stage 64-state plus comparison selection unit GACSU.

[0071] The calculation process of the 4-level addition and comparison selection unit ACSU is basically the same as that of the 3-level addition and comparison selection unit ACSU, except that in the first step, 4 sets of branch metric values ​​are required, and in the second step, 64 state additions need to be performed simultaneously. Calculation of the comparison unit GACSU.

[0072] The calculation process of the add ratio selection unit ACSU is described...

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Abstract

The invention discloses a cascading add-compare-select unit in a convolutional code Viterbi decoder and a data processing method thereof. For a (2,1,m) convolutional code, an add-compare-select unit (ACSU) adopts a cascading mode. The add-compare-select unit (ACSU) comprises n (n=2,3,4,...) single-stage 2m-1 state add-compare-select units (GACSU); and the single-stage 2m-1 state add-compare-select units (GACSU) comprise 2m-1 single-state add-compare-select units (SACSU). In the single-state add-compare-select units (SACSU), the input of each summer is a branch measure and a state value calculated by the (GACSU) at last time; and the input of a comparator is the minimum value of calculation results of the two summers. In the cascading add-compare-select unit, the decoder can perform add-compare-select calculation for a plurality of times within a clock period, increase the decoding speed rate under the condition of less hardware resources and realize high-speed decoding under a low-speed clock.

Description

technical field [0001] The invention belongs to the field of communication channel coding and decoding, in particular, it refers to a design method of cascade addition, comparison and selection units in a convolutional code Viterbi decoder. Background technique [0002] Convolutional codes have great applications in deep space communication and other fields. The decoding of convolutional codes is currently the most widely used Viterbi decoding algorithm. At present, the research on Viterbi decoding algorithms is mainly focused on the design of integrated circuits and FPGA implementation. Among them, the research on high-speed decoding accounts for the main part, mainly including decoding The fast processing of the coder surviving path and the fast calculation of the addition ratio selection, among which the research on the addition ratio selection calculation mainly focuses on the radix 2 after the grid graph is merged n Research on operational structures, etc. Base 2 n A...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M13/41
Inventor 刘荣科王闰昕赵岭
Owner BEIHANG UNIV