Semiconductor device having saddle fin transistor and method for fabricating the same

Abstract

A method for fabricating a semiconductor device includes forming a pad nitride layer that exposes an isolation region over a cell region of a semiconductor substrate; forming a trench in the isolation region of the semiconductor substrate; forming an isolation layer within the trench; etching an active region of the semiconductor substrate by a certain depth to form a recessed isolation region; etching the isolation layer by a certain depth to form a recessed isolation region; depositing a gate metal layer in the recessed active region and the recessed isolation region to form a gate of a cell transistor; forming an insulation layer over an upper portion of the gate; removing the pad nitride layer to expose a region of the semiconductor substrate to be formed with a contact plug; and depositing a conductive layer in the region of the semiconductor substrate to form a contact plug.

Description

[0001] related application [0002] This application claims priority from Korean Patent Application No. 10-2008-0134817 filed on December 26, 2008, the entire contents of which are incorporated herein by reference. technical field [0003] The present invention relates generally to semiconductor devices and methods of manufacturing the same, and more particularly to semiconductor devices and methods of manufacturing the same capable of preventing contact defects and overcoming process tolerance limitations by employing a damascene process and a saddle fin transistor structure. Background technique [0004] Recently, as the design rules of semiconductor devices are drastically reduced to technologies below 40 nm, the area of ​​active regions in which devices can be formed is also reduced. Therefore, there are various process tolerance limitations. In particular, the abnormal shape of the gate line, that is, the gate line slope or the gate line roughness becomes a serious pro...

AI Technical Summary

Problems solved by technology

[0006] However, the patterning of the linear recess structure and the increase of gate line tilt and gate line roughness cause an increase of contact defects in the self-aligned contact (SAC) process

Moreover, due to the reduction of the area where the device is to be formed and such contact defects, it is practically impossible to ensure the tolerance of the SAC process

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