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System and method for fast cache-hit detection

A technology for error detection and cache state, applied in the field of storage systems, can solve problems such as inability to correct errors, missing cache, etc., and achieve the effect of reducing actual state and power usage, and reducing logic complexity

Active Publication Date: 2012-07-04
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

If a DED occurs, the error bit corrector 269 may not be able to correct the error in the cache tag and a cache miss occurs

Method used

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  • System and method for fast cache-hit detection
  • System and method for fast cache-hit detection
  • System and method for fast cache-hit detection

Examples

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Embodiment Construction

[0037] The making and using of the preferred embodiment of the invention are described in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.

[0038] Embodiments will be described in the context of a computer system having a memory system that utilizes ECC, which provides single-bit error correction and double-bit error detection, and cache memories to help improve memory system performance. However, the present invention is also applicable to other computer systems having memory systems using ECC capable of correcting and detecting additional bit errors.

[0039] Figure 3a is a schematic diagram showing a detailed view of the cache access unit 300 . Such as Figure 3a As shown, cache access unit 300 may determin...

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Abstract

A system and method for fast detection of cache memory hits in memory systems with error correction / detection capability is provided. A circuit for determining an in-cache status of a memory address comprises an error detect unit coupled to a cache memory, a comparison unit coupled to the cache memory, a results unit coupled to the comparison unit, and a selection unit coupled to the results unitand to the error detect unit. The error detect unit computes an indicator of errors present in data stored in the cache memory, wherein the data is related to the memory address. The comparison unit compares the data with a portion of the memory address, the results unit computes a set of possible in-cache statuses based on the comparison, and the selection unit selects the in-cache status from the set of possible in-cache statuses based on the indicator.

Description

[0001] This application claims priority to US Provisional Patent Application No. 61 / 146,574, filed January 22, 2009, entitled "System and Method for Fast Cache-Hit Detection," which application is incorporated herein by reference. technical field [0002] The present invention relates generally to memory systems, and more particularly to systems and methods for fast detection of cache hits in memory systems with error correction / detection capabilities. Background technique [0003] In most modern computer systems, the storage system has a significant impact on the performance of the computer system. A poorly designed memory system can prevent a modern computer system with a state-of-the-art processing unit from performing processing any better than an older computer system with an average processing unit. This may be due to slower access to programs, applications, data, etc. stored in the storage system. A poorly designed memory system can significantly delay access to memo...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F11/10G06F12/08
CPCG06F11/0751G06F11/073G06F11/1064G06F12/0895Y02D10/00
Inventor 陈彝梓
Owner TAIWAN SEMICON MFG CO LTD
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