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Microprocessor and method for analyzing related instruction

A microprocessor and instruction technology, applied in the direction of concurrent instruction execution, machine execution device, etc., to achieve the effect of less delay

Active Publication Date: 2010-09-01
VIA TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Therefore, in terms of clock cycles, the call or return instruction has the same latency as other instructions

Method used

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  • Microprocessor and method for analyzing related instruction
  • Microprocessor and method for analyzing related instruction
  • Microprocessor and method for analyzing related instruction

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Embodiment Construction

[0019] In order to make the above and other objects, features, and advantages of the present invention more comprehensible, preferred embodiments are listed below and described in detail in conjunction with the accompanying drawings.

[0020] see figure 1 , is a block diagram showing a microprocessor 100 according to the present invention. Microprocessor 100 includes a fetch unit 104 that fetches program instructions from an instruction cache 106 . An instruction pointer register 112 provides a fetch address 168 to the instruction cache 106 . The fetch unit 104 fetches instructions from the fetch address 168 of the instruction cache 106 . The extracted program instructions may include user program instructions, such as an operating system or application program. The fetched instructions may include general instructions, including conditional branch instructions (hereinafter referred to as CB). Extracted commands also include quick call and return commands according to the ...

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Abstract

The invention provides a microprocessor and method for analyzing related instruction. The microprocessor having a plurality of call / return stacks (CRS) correctly resolves a call or return instruction rather than issuing the instruction to execution units of the microprocessor to be resolved. The microprocessor fetches a call or return instruction and determines whether the instruction is the first call or return instruction fetched after fetching a conditional branch instruction that has yet to be resolved. The microprocessor copies the contents of a current CRS to another CRS and designates the other CRS as the current CRS, if the state exists. The microprocessor pushes the address of the next sequential instruction following the call instruction onto the current CRS and fetches an instruction at the call instruction target address if the instruction is a call instruction. The microprocessor pops a second return address from the current CRS and fetches an instruction at the second return address, if the instruction is a return instruction.

Description

technical field [0001] This invention relates to microprocessors, and more particularly to the processing of call and return instructions in a pipelined microprocessor. Background technique [0002] Programs usually contain subroutine call instructions and return instructions from subroutines. A call command causes a program flow to change from the current program or instruction sequence to a different instruction sequence or program than the currently fetched and executed program. A call instruction specifies a call address or destination address, which is the address of the first instruction of the subroutine. In addition, the call instruction instructs the processor to store the address of the next instruction after the call instruction, which is called the return address. A return instruction also causes a program flow change to a different sequence of instructions than the currently fetched and executed program. However, a return instruction does not explicitly speci...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/38
Inventor 布兰特·比恩泰瑞·派克斯G·葛兰·亨利
Owner VIA TECH INC
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