Sense amplifier and memory with same

Abstract

A sense amplifier and a memory with the same, wherein a sense amplifier circuit includes a bit line, a sense amplifier output, a keeper circuit including an NMOS transistor and connected to a bit line, and a noise threshold control circuit. The keeper circuit is sized to supply sufficient current to compensate a leakage current of the bit line and maintains a voltage level of the bit line; the noise threshold control circuit is connected to the sense amplifier output and the bit line and lowers a trip point of the sense amplifier output; and the trip point is the highest voltage when the sense amplifier output is switched from a high electric level to a low electric level. The noise threshold control circuit with a strong NMOS transistor is connected in parallel with a conventional nand gate and the trip point of the sense amplifier output is reduced by properly reducing the beta value of the nand gate.

Description

technical field [0001] The present invention relates to a semiconductor device, also to a memory array, and more to the design and operation of a static random access memory (SRAM) array and a register file capable of sensing data in a bit cell by a single-ended sensing method. Background technique [0002] Static random access memory (SRAM) is commonly used in integrated circuits. The advantage of the SRAM lattice is that it can retain data without relying on the refresh action. SRAM cells can have different numbers of transistors, and are often named for the number of transistors they have, eg, 6TSRAM, 8TSRAM, etc. A transistor is usually used as a data latch to store a data bit, and other transistors are added to control the access of the transistor. SRAM cells are typically organized into arrays with multiple rows and columns. Generally, each row of the SRAM cell is respectively connected to a word line, and the purpose is to determine whether the SRAM cell being used...

AI Technical Summary

Problems solved by technology

However, this approach will make the circuit 100 more susceptible to noise near the high state voltage because the trip point is higher than before.

For example, when there is noise close to a high state at the bit line 108a or 108b, the output voltage may be lowered by noise below the trip point of the NAND gate 106, which will result in erroneous operation

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