Instruction execution method for vector complex multiplication operation and corresponding device

Abstract

The invention relates to an instruction execution method for vector complex multiplication operation (a+bj)*(c+dj) in a processor and a corresponding device. The method is characterized by comprising the step of designing two instruction matching pairs to finish the vector complex multiplication operation (a+bj)*(c+dj), wherein the first instruction executes vector multiplication, and the operation numbers of the first instruction comprise (a+bj) and (c+dj) for calculating partial results of the vector complex multiplication operation (a+bj)*(c+dj); and the second instruction executes vector multiplication and addition, and the operation numbers of the second instruction comprise the (a+bj), the (c+dj) and execution results of the first instruction for calculating rest results of the vector complex multiplication operation (a+bj)*(c+dj) and adding the rest results and the partial results to obtain a final result of the vector complex multiplication operation (a+bj)*(c+dj). By designing the two instruction matching pairs to finish the operation, the flow length of the vector complex multiplication operation is a flow grade of the multiplication and addition operation. Moreover, the method can greatly save the area and cost of a chip by complexing vector multiplication and addition functional components of the two instructions.

Description

technical field [0001] The invention relates to the technical field of microprocessor architecture, in particular to an instruction execution method and a corresponding device for multiplication operation of vector complex numbers. Background technique [0002] With the continuous development of processor technology, the field of its application is also expanding. In order to meet the needs of high-end applications such as high-performance computing and digital signal processing, combined with the technical trend of the integration of general-purpose CPU (central processing unit) and DSP (digital signal processor), more and more general-purpose processors are used in fast Fourier Fields such as leaf transform (FFT), filtering (FIR) and other data-intensive calculations for dedicated digital signal processing. The field of data-intensive computing puts forward higher and higher requirements on the data processing capability of the chip, and all kinds of general-purpose proce...

AI Technical Summary

Problems solved by technology

The disadvantages of this implementation method are: 1. The number of pipeline stages is long, and the pipeline start-up time is long, which easily leads to insufficient instruction windows and blockage of each control queue; 2. Multiplication and addition are separate arithmetic units, which increases the area of ​​the processor. , which increases the hardware implementation cost of the processor; and 3. In order to increase the peak value of the vector complex multiplication operation, it is necessary to increase the corresponding operation function components in parallel, so that the increase in the implementation cost after the instruction vectorization is more obvious

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