Power-down retaining circuit, method and power supply system

Abstract

The invention provides power-down retaining circuit and method and a power supply system. The circuit comprises an energy storage capacitor, a voltage reduction circuit and a voltage booster circuit, wherein the first input end and the second input end of the voltage reduction circuit are respectively connected with the anode and the canoed of an input power supply, the first output end and the second output end of the voltage reduction circuit are respectively connected with the anode and the canoed of the energy storage capacitor for reducing the input voltage of the input power supply when the input power supply is normal, the energy storage capacitor is charged by the output of the voltage reduction circuit, the first input end and the second input end of the voltage booster circuit are respectively connected with the anode and the canoed of the energy storage capacitor for boosting the energy storage voltage of the energy storage capacitor when the input power supply is powered down, and the energy storage capacitor is used for finishing a charging process by the reduced input voltage when the input power supply is normal and is also used for supplying power to an output load by the boosted energy storage voltage when the input power supply is powered down. The embodiment of the invention realizes a long period of power-down protection time when a low voltage is input.

Description

technical field [0001] The embodiments of the present invention relate to the field of electronic technology, and in particular, to a power-fail holding circuit, method and power supply system. Background technique [0002] With the continuous development of the power supply business, products have higher and higher requirements for the continuous stability of the power supply. Especially when the input network voltage drops abnormally, the system needs to quickly report and store the system operation status and abnormal network voltage within the power-off hold time, and switch to the backup power supply mode. Therefore, in order to achieve the purpose of power-down retention, it is necessary to set a power-down retention circuit in the power supply system, and it is necessary to extend the power-down retention time as much as possible. [0003] In the prior art, a boost topology is usually used to prolong the power-down time. at input voltage V 1 Normally, the input vol...

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Problems solved by technology

[0006] In the process of realizing the present invention, the inventors found that there are at least the following problems in the prior art: since the capacitor itself has a derating requirement for the withstand voltage value of the capacitor, when the range of the input voltage is wide, the higher withstand voltage value and the limited The layout space becomes the bottleneck for selecting large-capacity capacitors, which makes the selection of capacitors difficult; and when the input voltage is low, it is impossible to achieve a long power-off protection time

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