Semiconductor wafer having pre-aligning pattern and method for pre-aligning the same

A semiconductor and pre-alignment technology, applied in the fields of semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc., can solve problems such as poor pre-alignment errors, and achieve the effect of easy confirmation

A semiconductor and pre-alignment technology, applied in the fields of semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc., can solve problems such as poor pre-alignment errors, and achieve the effect of easy confirmation

CN101986427AInactive Publication Date: 2011-03-16TAIWAN SEMICON MFG CO LTD
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  • Semiconductor wafer having pre-aligning pattern and method for pre-aligning the same
  • Semiconductor wafer having pre-aligning pattern and method for pre-aligning the same
  • Semiconductor wafer having pre-aligning pattern and method for pre-aligning the same

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Embodiment Construction

[0026] Hereinafter, each embodiment is described in detail and examples accompanied by drawings are used as a reference basis of the present invention. In the drawings or descriptions in the specification, the same reference numerals are used for similar or identical parts. And in the drawings, the shapes or thicknesses of the embodiments may be enlarged, and marked for simplicity or convenience. In addition, the parts of each element in the drawings will be described separately. It should be noted that the elements not shown or described in the drawings are forms known to those of ordinary skill in the art. In addition, specific embodiments are only disclosed The specific mode used in the present invention is not intended to limit the present invention.

[0027] Embodiments of the present invention provide a wafer pre-alignment method in integrated circuit technology to reduce pre-alignment errors. Like reference numerals are used to refer to like elements throughout the il...

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Abstract

The present invention discloses a semiconductor wafer having a pre-aligning pattern and a method for pre-aligning the same. The semiconductor wafer has the pre-alignment pattern including two or more notches on the wafer edge and the notches are used for wafer pre-alignment in fabrication processes. In one embodiment, at least two distances along the wafer edge between any adjacent notches are different. In another embodiment, distances along the wafer edge between any adjacent notches are each different. In another aspect, the pre-alignment pattern includes one or more notches on the wafer edge and one flat side on the wafer edge, wherein the notches and the flat side are used for wafer pre-alignment in fabrication processes. In one embodiment, at least two distances along the wafer edge between any adjacent notches or between the flat side and an adjacent notch are different. In another embodiment, distances along the wafer edge between any adjacent notches and between the flat side and an adjacent notch are each different. According to the invention, an pre-aligning error can be reduced.

Description

technical field [0001] The present invention relates to a method for manufacturing integrated circuits, and more particularly to a method for pre-aligning semiconductor wafers using notches and / or flat edges. Background technique [0002] In integrated circuit (IC) processing, an alignment step is a step in a photolithographic process in which a layer of the circuit is patterned using a mask whose x-y position corresponds to the wafer on which the circuit is to be formed (e.g. silicon wafers). Through the alignment step, the mask (or photomask) in the photolithography process is positioned relative to the wafer before the photoresist is exposed. Thus, the pattern on the mask overlaps the pattern previously formed on the wafer surface. The pattern used for alignment is called an alignment mark, which is a specially configured mark placed on each mask to allow precise alignment between the mask and the pattern on the wafer. [0003] The pre-alignment step is a preliminary a...

Claims

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Application Information

Patent Timeline
16 Mar 2011
Publication
CN101986427A
IPC
H01L23/544; H01L21/68
CPC
G03F9/7084; H01L21/68; G03F9/7011
Inventors
王盈盈