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Three-dimensional semiconductor memory device

A storage device and semiconductor technology, applied in the fields of semiconductor devices, semiconductor/solid-state device manufacturing, and semiconductor/solid-state device components, etc., can solve problems such as reduced product reliability and reduced operating speed

Active Publication Date: 2015-04-01
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, this new structure poses various problems, such as reduced reliability and / or reduced operating speed of the product

Method used

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  • Three-dimensional semiconductor memory device
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  • Three-dimensional semiconductor memory device

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no. 2 example

[0143] The same reference numerals are used to denote the same components as those in the first embodiment of the present inventive concept, and descriptions of the same components will be omitted for brevity.

[0144] Figure 12 is a perspective view illustrating a unit semiconductor memory device according to a second embodiment of the inventive concept. Figure 13 yes Figure 12 The top view of the three-dimensional semiconductor memory device shown in . Figure 14 is a plan view illustrating a modified example of the three-dimensional semiconductor memory device according to the second embodiment of the inventive concept.

[0145] refer to Figure 12 and 13 , the three-dimensional semiconductor memory device may include a reference figure 1 , 2A -2E and image 3Vertical strings, conductor 150a, bit lines 145a and 145b, local interconnects 147a and 147b, and second interlevel dielectric layer 152 are depicted. A plurality of interconnects 260 a and 260 b may be disp...

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PUM

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Abstract

Provided is a three-dimensional semiconductor memory device. The three-dimensional semiconductor memory device includes a substrate that has a cell array region including a pair of sub-cell regions and a strapping region interposed between the pair of sub-cell regions. A Plurality of sub-gates are sequentially stacked on the substrate in each of the sub-cell regions, and interconnections are electrically connected to extensions of the stacked sub-gates, respectively, which extend into the strapping region. Each of the interconnections is electrically connected to the extensions of the sub-gate which are disposed in the pair of the sub-cell regions, respectively, and which are located at the same level.

Description

[0001] This application claims priority from Korean Patent Application No. 10-2009-0110975 filed with the Korean Intellectual Property Office on Nov. 17, 2009, the disclosure of which is hereby incorporated by reference. technical field [0002] The present invention relates to semiconductor devices, and more particularly, to three-dimensional semiconductor memory devices. Background technique [0003] With the rapid development of the electronics industry, the requirements for the integration of semiconductor storage devices are also increasing. The degree of integration is an important factor in determining the price of a product. For example, as the degree of integration increases, the price of semiconductor memory devices decreases. For this reason, semiconductor devices in particular require a higher degree of integration. In general, since the degree of integration of a semiconductor device can be determined by a two-dimensional area of ​​a unit memory cell, the degr...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/105H01L23/528H10B10/00
CPCH01L21/02697H01L27/11582H01L27/11565H01L27/11578H01L21/02365H10B43/10H10B43/50H10B43/20H10B43/27H01L29/7841
Inventor 沈善一许星会金汉洙张在薰赵厚成
Owner SAMSUNG ELECTRONICS CO LTD