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High-speed coding method of LDPC and shortened codes thereof

A decoding and high-speed technology, applied in the field of encoding and decoding, can solve the problems of high hardware implementation platform cost, low computing speed, unfavorable large-scale application, etc., achieve optimal decoding effect, increase operating frequency, and save chip resource occupation.

Active Publication Date: 2013-09-18
牛毅
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  • Abstract
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The current hardware implementation of LDPC decoding is mostly based on code patterns with short code lengths (code lengths of tens to hundreds of bits), and the calculation rate is low (tens of megabytes to tens of megabytes), and due to the limitation of hardware resources , the implementation of a powerful LDPC decoder requires a chip with good performance, and even needs to be specially designed for a specific algorithm. The cost of hardware implementation platform is very high, which is not conducive to large-scale application

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  • High-speed coding method of LDPC and shortened codes thereof
  • High-speed coding method of LDPC and shortened codes thereof
  • High-speed coding method of LDPC and shortened codes thereof

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Embodiment Construction

[0025] The present invention will be further described below in conjunction with the accompanying drawings.

[0026] The decoding algorithms of LDPC codes are:

[0027] 1. SPA (Sum-Product Algorithm), Probability-domain;

[0028] 2. SPA, Log-domain;

[0029] 3. Min-sum (simplified algorithm of Log-domain SPA), and its various revised versions;

[0030] 4. BF (Bit-Flipping);

[0031] 5. MLG (Majority-Logic), can only be applied to cyclic LDPC codes.

[0032] For the algorithms listed above, the complexity and bit error performance decrease in order. Among them, the Probability-domainSPA calculation is too complicated, and the BF algorithm and the MLG algorithm cannot provide good bit error performance, and are not suitable for use in practice. Among the several algorithms that can be used, the error performance of the modified Min-sum algorithm can be close to that of SPA, and the complexity is relatively low. Therefore, after comprehensive consideration, the modified Min-...

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Abstract

The invention discloses a high-speed coding method for LDPC (low-density parity-check) codes and shortened codes thereof. The method adopts the standard code types (8176 and 7154) established by CCSDS (consultative committee for space data system), realizes the coding of high-speed data stream on a hardware platform with lower cost, and enables low-density parity-check code with long length to be coded under the station of high code rate.

Description

technical field [0001] The invention belongs to the technical field of coding and decoding, and relates to a high-speed decoding device for LDPC and shortened codes thereof. Background technique [0002] LDPC code was first proposed by Gallager in his doctoral dissertation in the 1960s, but it was limited by the technical conditions at that time and lacked a feasible decoding algorithm. It was basically ignored in the following 35 years, and it was promoted by Tanner in 1981. LDPC (Low Density Parity Check Code) codes and gives the graph representation of LDPC codes, which is later called Tanner graph. In 1993, Berrou et al. discovered Turbo codes. On this basis, around 1995, MacKay and Neal et al. re-studied LDPC codes and proposed a feasible decoding algorithm, thus further discovering the good performance of LDPC codes. , quickly aroused strong repercussions and great attention. At present, it has been widely used in deep space communication, optical fiber communication...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M13/11
Inventor 牛毅马忠松傅得立
Owner 牛毅