Phase lock loop (PLL) device and control method thereof

Abstract

The invention discloses a phase lock loop (PLL) device and a control method thereof. The PLL device comprises a PLL circuit and a storage unit, wherein, the PLL circuit generates a phase lock clock signal according to a control voltage; and the storage unit is coupled with the PLL circuit and provides an initial signal to the PLL circuit according to a digital value when the PLL circuit is started so as to restore the control voltage to a preset value.

Description

technical field [0001] The invention relates to a phase-locked loop device, in particular to a phase-locked loop device with short locking time. Background technique [0002] Figure 1A is a schematic diagram of a known phase lock loop (Phase lock loop; PLL) device. The PLL device 10 includes a phase detector (Phase detector) 11, a charge pump (Charge pump) 12, a loop filter (Loop filter) 13, a voltage controlled oscillator (Voltage control oscillator; VCO) 14 and a frequency divider ( Divider) 15. The frequency divider 15 divides the phase-locked clock signal produced by the voltage-controlled oscillator 14 and feeds it back to the phase detector 11. The phase detector 11 provides a control signal to the charge mercury 12 according to the phase detection result to generate a control current. The capacitors C1 and C2 are charged and discharged via the loop filter 13 , and a voltage Vc is generated on the node 132 , which is provided to the voltage-controlled oscillator 14 ...

AI Technical Summary

Problems solved by technology

The phase-locked loop device 10 needs a period of locking time every time it starts to lock the frequency of its signal, and charges the voltage on the node 132 to the target value, and generally starts charging from 0V or VDD. Please also refer to Figure 1B , taking charging from 0V as an example here, when the voltage on the node 132 is slowly charged from zero and reaches the preset target voltage Vc, the phase-locked clock signal output by the phase-locked loop device 10 reaches the target value Fvco and locks frequency, before reaching frequency locking, it is necessary to go through a locking time of length t1, so the known phase-locked loop device 10 needs to go through a lengthy locking time to reach frequency locking every time it is started, which slows down the speed of the entire system

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