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Method, system and design structure for unifying voltage environment of reused sub modules in chip design

A sub-module voltage and chip design technology, applied in computer-aided design, CAD circuit design, calculation, etc., can solve the difficult problems of reusing sub-module timing differences and time-consuming problems

Inactive Publication Date: 2013-10-23
GLOBALFOUNDRIES INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0006] However, these methods are not only time-consuming, but also difficult to solve the timing difference between reused sub-modules. For a complex design, this part of the work will account for 10% to 20% of the work time in the final stage.

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  • Method, system and design structure for unifying voltage environment of reused sub modules in chip design
  • Method, system and design structure for unifying voltage environment of reused sub modules in chip design
  • Method, system and design structure for unifying voltage environment of reused sub modules in chip design

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Embodiment Construction

[0025] Preferred embodiments of the invention will be described in more detail with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. However, the present invention may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0026] When using the hierarchical design method to design the chip, each sub-module has an independent power ring (power ring) around the edge of the sub-module. The external power mesh is directly connected to the power ring, and the devices inside the reused sub-module are all powered by the power ring. When the top-level design calls reused submodules multiple times, the ambient voltage of each submodule is not the same, figure 1 An example of three reused submodules with different a...

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Abstract

The invention discloses a method, a system and a designed structure for making the voltage environment of reused submodules consistent in chip design, wherein each reused submodule is connected to the power supply network of the chip through a power supply connection point on its power supply ring , the method includes: adjusting the number and position of the power supply connection points of the multiple reused submodules, so that the number of the power supply connection points of the multiple reused submodules is the same as the corresponding position of the power supply connection point; adjusting the multiple The power lines on the power supply network connected to the power supply connection points of the reused submodules make the voltages on the power supply connection points corresponding to the multiple reused submodules consistent. The invention can reduce the timing difference of the reused sub-modules in the chip design, and ultimately achieve the purpose of reducing design complexity and workload, and reducing the design cycle.

Description

technical field [0001] Various embodiments of the present invention generally relate to chip design, and more specifically, various embodiments of the present invention relate to a method, system and design structure for making voltage environments of reused sub-modules consistent in chip design. Background technique [0002] At present, the scale of integrated circuits is becoming larger and larger, the technology is becoming more and more advanced, and the design itself is becoming more and more complex. Hierarchical design is the most commonly used design method for integrated circuit chips. In this design method, the chip to be designed is divided into many sub-modules, and each sub-module is designed separately and then called by the top layer. If several sub-modules in the design are exactly the same, you only need to design the sub-module once, and complete the design of the entire chip by calling the designed sub-module multiple times during the top-level design. Suc...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/50
CPCG06F30/3312G06F2115/08G06F2119/06
Inventor 汤晓峰徐晨唐佳廉李侠
Owner GLOBALFOUNDRIES INC