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SAD (sum of absolute difference) vectorization realization method oriented to vector processor

A technology of a vector processor and an implementation method, which is applied to the implementation field of SAD vectorization, can solve the problems of a large amount of calculation, a single chip cannot meet application requirements, etc., and achieves the effects of low cost, shortened operation time, and convenient operation.

Active Publication Date: 2013-03-27
NAT UNIV OF DEFENSE TECH
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  • Abstract
  • Description
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  • Application Information

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Problems solved by technology

[0002] Image matching processing applications in the field of image processing require many high-density computing applications, such as template-based image matching often need to calculate the absolute value of the difference (Sum of Absolute Difference, SAD), etc., such high-intensity computing tasks need to combine the template image with Each sub-image traversed by pixels in the real-time image is matched and calculated one by one. The amount of calculation is very large, and it is difficult for a single chip to meet the application requirements. Based on multi-core processors, especially vector processors, the speed of image matching can be greatly improved.

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  • SAD (sum of absolute difference) vectorization realization method oriented to vector processor
  • SAD (sum of absolute difference) vectorization realization method oriented to vector processor
  • SAD (sum of absolute difference) vectorization realization method oriented to vector processor

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Embodiment Construction

[0030] The present invention will be described in further detail below in conjunction with the accompanying drawings and specific embodiments.

[0031] Such as figure 1 Shown, the vector processor-oriented SAD vectorization implementation method of the present invention comprises the following steps:

[0032] 1. Let the real-time graph A be MxN in size, the template graph B be mxn in size, and M>m, N>n; the vector processor includes P processing units.

[0033] 2. The vector processor traverses the real-time graph A and accesses the sub-graph A whose two headers in the real-time graph A are separated by 4 elements and whose vector length is 4*p uv and A (u+4)v , through the shuffling operation, 4 adjacent subgraphs A with a head interval of 1 element and a length of 4*p are obtained (u+k)v (k=0, 1, 2, 3).

[0034] Such as figure 2 As shown, taking the number of PEs equal to 2 as an example to illustrate how to obtain 4 adjacent subgraphs whose heads are separated by 1 el...

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Abstract

The invention discloses an SAD (sum of absolute difference) vectorization realization method oriented to a vector processor, and the method comprises the following steps: setting a real time image A which is M*N in size, setting a template image B which is m*n in size, wherein M>m, and N>n; transversing the real time image A, storing two sub-images Auv and A(u+4)v which are spaced by 4 elements with the vector length of 4*p in the real time image A, and obtaining 4 adjacent sub-images A(u+k)v (k=0,1,2,3) through shuffling; taking a sub-image with the vector length of 4*p from the template image B; respectively calculating the SAD coefficient values p(u, v), p(u, v+1), p(u, v+2), p(u, v+3) of A(u+k)v (k=0,1,2,3) and the template image B; and assuming u=u+4, repeating the previous steps until the real time image A is transversed completely, and obtaining all the SAD coefficient values of the image A and template B through calculation.

Description

technical field [0001] The invention relates to the fields of vector processors and image processing, in particular to a method for realizing SAD vectorization. Background technique [0002] Image matching processing applications in the field of image processing require many high-density computing applications, such as template-based image matching often need to calculate the absolute value of the difference (Sum of Absolute Difference, SAD), etc., such high-intensity computing tasks need to combine the template image with Each pixel-traversal sub-image in the real-time image is matched and calculated one by one. The amount of calculation is very large, and it is difficult for a single chip to meet the application requirements. Based on multi-core processors, especially the vector processor, the speed of image matching can be greatly improved. Vector processors generally consist of multiple processing elements (PEs) and typically support vector-based data loads and stores. ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06T1/20
Inventor 刘仲陈书明刘衡竹陈跃跃陈海燕龚国辉孙永节万江华吴家铸陈胜刚
Owner NAT UNIV OF DEFENSE TECH