Semiconductor chip and semiconductor package with stacked chip structure

Abstract

A semiconductor chip and semiconductor package with stack chip structure include align patterns. The align patterns are formed of magnetic materials having opposite polarities on the top and bottom of the semiconductor chip. Thus, when the plurality of chips are stacked on the substrate in order for the packaging, the semiconductor chips may be exactly aligned by the magnetic force between the align patterns of the vertically stacked chips. The semiconductor package includes a plurality of stacked semiconductor chips and a filling material. Each of the stacked semiconductor chips includes a semiconductor substrate having a first surface and a second surface, wherein a circuit pattern such as a bonding pad is formed on the first surface, and a first align pattern formed on the first surface of the semiconductor substrate, wherein the first align pattern is formed of a magnetic material.

Description

technical field [0001] Exemplary embodiments of the present invention relate to a semiconductor package, and more particularly, to a semiconductor chip applicable to a stacked chip package, and a semiconductor package having a stacked chip structure. Background technique [0002] Recently, with the increasing demand for small, high-performance and mobile electronic products, the demand for ultra-small, high-capacity semiconductor memory devices is increasing. In general, the storage capacity of a semiconductor memory device can be increased by a method of increasing the integration degree of a semiconductor chip or a method of mounting and assembling a plurality of semiconductor chips in a single semiconductor package. The former requires a lot of energy, capital and time, while the latter can easily increase the storage capacity of the semiconductor memory by changing the packaging method. In addition, compared with the former, the latter is more favorable in terms of requ...

AI Technical Summary

Problems solved by technology

If the substrate is warped, it is more difficult to align the TSVs accurately

If misalignment occurs between these TSVs or distortion of the substrate occurs, the conductive metal used to transmit and receive signals may be destroyed or electrically shorted

As a result, the chip may not function properly

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