Semiconductor device and manufacturing method thereof
A manufacturing method, semiconductor technology, applied in the direction of semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., can solve problems such as increased debris, decreased product qualification rate, and inability to realize the dam function, so as to avoid the process The effect of increasing the number and reducing the manufacturing cost
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no. 1 approach
[0132] Hereinafter, the first embodiment will be described. figure 1 It is a plan view showing the semiconductor device exemplified in this embodiment, figure 2 yes means figure 1 A diagram of the cross-sectional structure of the II-II' line. Here, a case is shown in which a plurality of chip regions 12 and scribe regions 13 for separating each chip region 12 by dicing are formed on a wafer.
[0133] A semiconductor device is formed using a substrate 11 . A laminated insulating film 70 having a structure in which a plurality of interlayer insulating films 15 , 16 , 17 , 18 , 19 , and 20 are sequentially stacked from bottom to top is formed on substrate 11 .
[0134] In the chip region 12 , an active layer 30 constituting an element (not shown in the figure) is formed on the upper portion of the substrate 11 , and a wiring structure 71 connected to the active layer 30 is formed in the laminated insulating film 70 . The wiring structure 71 includes: the via hole 31 formed...
no. 2 approach
[0168] Next, a second embodiment will be described. Figure 9 It is a plan view showing the semiconductor device exemplified in this embodiment, Figure 10 yes means Figure 9 The diagram of the cross-sectional structure of the X-X' line in the middle. As in the case of the first embodiment, a case where a plurality of chip regions 12 and scribe regions 13 for separating each chip region 12 by dicing are already formed on the wafer is shown.
[0169] Below, the main Figure 9 and Figure 10 The structure of the semiconductor device shown with figure 1 and figure 2 Differences in the configuration of the first embodiment shown will be described. It should be noted that the same symbols are used for the same components.
[0170] In the case of this embodiment, if Figure 9 and Figure 10 As shown, the passivation film 22 is formed on the portion other than the pad electrode 37 portion. Further, in order to protect the chip region 12 , a protective film 23 having open...
no. 3 approach
[0183] Next, a third embodiment will be described. Figure 12 It is a plan view showing the semiconductor device exemplified in this embodiment, Figure 13 yes means Figure 12 A diagram of the cross-sectional structure of the XIII-XIII' line. As in the case of the first embodiment, a case where a plurality of chip regions 12 and scribe regions 13 for separating each chip region 12 by dicing are already formed on the wafer is shown.
[0184] Below, the main Figure 12 and Figure 13 The structure of the semiconductor device shown with figure 1 and figure 2 Differences in the configuration of the first embodiment shown will be described. The same symbols are used for the same constituent elements.
[0185] In the case of this embodiment, if Figure 13 As shown, the passivation film 21 also has an opening above the sealing ring 14 in addition to the opening above the wiring structure 71 . A cover layer 47 is formed in the opening, and the cover layer 47 is connected t...
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