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Semiconductor transistor structure and making method thereof

A technology of transistors and semiconductors, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electric solid-state devices, etc., can solve problems such as band-band tunneling, impurity distribution changes, and impurity diffusion

Inactive Publication Date: 2013-02-06
INST OF SEMICONDUCTORS - CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

On the one hand, it is easy to lead to band-band tunneling; on the other hand, it requires a sharp change in the doping concentration at both ends of the channel within a distance of several nanometers, that is, a very high concentration gradient, which brings challenges to the annealing after ion implantation, because Annealing causes impurity diffusion and changes in impurity distribution

Method used

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  • Semiconductor transistor structure and making method thereof
  • Semiconductor transistor structure and making method thereof
  • Semiconductor transistor structure and making method thereof

Examples

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preparation example Construction

[0058] See Figure 5-Figure 23 As shown, the present invention provides a method for manufacturing a semiconductor transistor structure, including the following steps:

[0059] Step 1: Select silicon-on-insulator 10 and dope the top silicon 12, the doping type is N-type or P-type, and the doping concentration is 1×10 15 cm -3 -1×10 21 cm -3 ;

[0060] Step 2: Growing a layer of SiO on the surface of the top silicon 12 by thermal oxidation 2 Hard mask 13; of which SiO 2 The thickness of the hard mask 13 is 10-50 nanometers;

[0061] Step 3: Through photolithography and SiO 2 Etching, predefine the device area on the SiO2 hard mask 13, and predefine the SiO after the device area 2 Hard mask 13 includes source SiO 2 Hard mask 131, drain SiO 2 Hard mask 132 and channel area fin structure SiO 2 Hard mask 133, SiO 2 The area where the hard mask 13 is etched away exposes the top layer silicon 12;

[0062] Step 4: By low pressure chemical vapor deposition on SiO 2 The hard mask 13 and the exp...

example

[0080] See Figure 1-Figure 4 As shown, a semiconductor transistor structure of the present invention includes:

[0081] A silicon-on-insulator 10, the silicon-on-insulator 10 includes a buried oxygen layer 11 and a top silicon 12, wherein the buried oxygen layer 11 has a thickness of 200 nm, the top silicon 12 has a thickness of 90 nm, and the top silicon 12 has a crystal plane of (110 ), there is a recess 111 in the middle of the top silicon 12, and the two sides of the recess 111 are the source 121 and the drain 122 of the top silicon 12 respectively. The source 121 and the drain 122 are connected by 25 silicon fin-like structures 123 A channel is formed. The source 121, drain 122, and silicon fin structure 123 of the top silicon 12 are all doped with P-type boron; the surface of the source 121, drain 122, and silicon fin structure 123 of the top silicon 12 Make a SiO 2 Dielectric layer 124; the doping concentration of the source region 121 and the drain region 122 of the top ...

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Abstract

The invention relates to a semiconductor transistor structure, which comprises a silicon-on-insulator, a gate conductive bar, a drain electrode, a source electrode and a gate electrode, wherein the silicon-on-insulator comprises a buried oxide layer and a top silicon layer; the middle part of the top silicon layer is provided with a concave part; the two sides of the concave part are respectivelya source region and a drain region of the top silicon layer; the source region and the drain region are connected through a plurality of silicon fin-shaped structures to form a channel; the source region and the drain region of the top silicon layer and the silicon fin-shaped structures are the same doping types; the gate conductive bar is made in the concave part and wraps the silicon fin-shapedstructures; the drain electrode is made on the drain region of the top silicon layer; the source electrode is made on the source region of the top silicon layer; and the gate electrode is made on thegate conductive bar.

Description

Technical field [0001] The invention relates to a semiconductor device, in particular to a semiconductor fin-shaped channel transistor (FinFET) structure and a manufacturing method thereof. Background technique [0002] With the continuous advancement of integrated circuit manufacturing technology, the feature size of metal-oxide-semiconductor field effect transistors (MOSFET) has been as small as tens of nanometers. One of the problems facing the continued shrinking of devices is the short channel effect and the resulting increase in static power consumption of the chip. [0003] Multi-gate fin-channel transistors (FinFETs) are expected to overcome this effect, allowing the device size to continue to shrink. Multi-gate FinFET replaces the planar channel of a conventional MOSFET with its fin-shaped channel, covering multiple surfaces of each fin-shaped channel with the gate, so that the gate controls the fin-shaped channel from multiple directions. The coupling effect of the elec...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/12H01L29/78H01L21/84H01L21/336
Inventor 张严波韩伟华杜彦东李小明陈艳坤杨香杨富华
Owner INST OF SEMICONDUCTORS - CHINESE ACAD OF SCI