A method, device and system for interconnecting wires and arbitration buses

Abstract

The embodiment of the present invention discloses a method, device and system for interconnecting a line with an arbitration bus. The device includes: a circuit mode controller and a logic multi-input AND gate; wherein the circuit mode controller is used to control the circuit in normal mode and Switching between self-test modes; the logic multi-input AND gate is used to perform logic AND operation on output signals when the circuit works in self-test mode, and output the operation result, so that the circuit can realize wired-AND arbitration. The method, device and system provided by the embodiments of the present invention realize the configurable interconnection of line and arbitration devices in the chip through logic multi-input AND gates, and can control the isolation of devices on the bus and the bus.

Description

technical field [0001] The embodiments of the present invention relate to the communication field, and in particular to a method, device and system for interconnecting a line and an arbitration bus. Background technique [0002] The wired and arbitrated bus is a simple and convenient multi-master bus system. Widely used in multi-host systems such as I2C (The Inter-Integrated Circuit, a serial bus protocol standard), CAN (ControllerArea Network, controller area network). This technology utilizes the line-AND characteristic of a single line to solve the arbitration problem when there are multiple drivers on the bus. [0003] The prior art uses open-drain pins or tri-state pins to implement the wired-AND feature. The following takes the I2C bus connection as an example to illustrate. figure 1 11 and 12 in are two I2C devices connected to the line and the arbitration bus respectively, and more can also be connected. The arbitration bus includes SDA (Serial Data Line, serial ...

AI Technical Summary

Problems solved by technology

[0009] Due to the implementation problems of pull-up resistors, open drains, and bidirectional buses, the above-mentioned line and interconnection schemes cannot be integrated in the chip, and the bus cannot be configured online, so the controllable isolation of devices on the bus and the bus cannot be realized.

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