Method for accelerating analysis and optimization of physical layout of integrated circuit

Abstract

The invention discloses a method for accelerating analysis and optimization of a physical layout of an integrated circuit, relating to the technical field of integrated circuits. The method comprises the following steps of: executing region division on the physical layout based on calculation nodes according to input data of the physical layout of the integrated circuit, executing isomorphic analysis on the regions in different calculation nodes, determining the analysis sequences of same regions in each calculation node and among the calculation nodes, analyzing and optimizing the regions of the physical layout according to the sequences, and multiplexing the analyzed and optimized results of the isomorphic regions among the calculation nodes during the analysis and optimization. According to the method for accelerating the analysis and optimization of the physical layout of the integrated circuit disclosed by the invention, the physical layout is divided by utilizing a multi-stage region segmentation algorithm, and the divided regions are analyzed by utilizing an isomorphic analysis method to find out the same regions in the divided regions, so that the posterior regions to be analyzed and optimized in the time sequence are not calculated any more, while the calculation results of the prior regions which are totally same as the posterior regions in the time sequence are multiplexed directly, thus the time is saved and the speed is increased.

Description

technical field [0001] The invention relates to the field of integrated circuits, in particular to a method for accelerating the analysis and optimization of the physical layout of integrated circuits based on region segmentation and region isomorphism. Background technique [0002] In system-on-chip integrated circuit design, the physical layout data capacity ranges from a few GB to hundreds of GB. With such a large amount of content, analysis and optimization (such as manufacturing-oriented design, parasitic parameter extraction, etc.) take a lot of time . [0003] The analysis and optimization of existing massive physical layouts generally adopt simple region segmentation methods, such as figure 1 As shown, first receive the physical layout data of the integrated circuit; then divide the physical layout into regions; deliver different regions to different computing nodes; analyze and optimize the allocated regions by each computing node; then output the physical layout a...

AI Technical Summary

Problems solved by technology

[0004] In order to solve the problem of slow and time-consuming data processing of the physical layout of integrated circuits in the prior art, the present invention provides a computer-aided method for the physical layout design of integrated circuits, using region division, region isomorphism and calculation multiplexing to Methods for increasing the speed of IC layout analysis and optimization, including:

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