Caching system and method of data caching

Abstract

The embodiment of the invention discloses a caching system and a method of data caching. The system comprises a high-speed interface, a cache group, a lower-speed interface, a status register, and a command sequence with conditions, wherein the command sequence with conditions is used for controlling the idle high-speed interface and low-speed interface to execute data caching according to caching conditions by the control command, and the caching conditions comprise data read-in conditions and data reading conditions; the data read-in conditions are that a cache in an empty status exists, and the data reading conditions are that a cache in a full status exists; and the high-speed interface and the low-speed interface are used for reading the caching conditions and cache statuses when the high-speed interface and the low-speed interface are in an idle status, judging whether the caching conditions are met according to the cache statuses, executing data caching and simultaneously updating the cache statuses when the caching conditions are met, and the status register is used for storing the status of each cache of the high-speed interface and the low-speed interface. According to the embodiment of the invention, the transmission rate of data between the high-speed interface and the low-speed interface can be improved.

Description

technical field [0001] The present application relates to the technical field of data storage, in particular to a cache system and a data cache method. Background technique [0002] When data is transmitted between two modules whose read and write speeds do not match, or between two modules working in different clock domains, a buffer circuit is usually used to buffer the transmitted data, so that the slow module Get the highest possible data transfer rate. For example, when a computer with a high-speed interface accesses a low-speed device with a low-speed interface such as an external memory or a printer, because the read and write speeds between the high-speed interface and the low-speed interface do not match, the high-speed device and the low-speed device need to be set. A cache device buffers data transferred between the two. [0003] Generally, data caching methods include ping-pong caching and circular caching. Wherein, the circular cache device adopts a plurality...

AI Technical Summary

Problems solved by technology

However, the speed of each channel on the low-speed interface side is usually inconsistent. For example, in a flash memory system, whether there is an error in the flash memory data, as well as the number of errors and the location of the error will cause different error correction times, resulting in the same The speed of the channel will also change over time, and eventually the speed between the channels will not be the same

At this time, when continuing to apply the circular buffer method based on the multi-channel low-speed interface in the prior art for data caching, the transmission rate of data is low when the data is transmitted between the high-speed interface and the low-speed interface

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